A 0.15-µm FD-SOI Substrate Bias Control SRAM with Inter-Die Variability Compensation Scheme

Shunsuke OKUMURA
Hidehiro FUJIWARA
Kosuke YAMAGUCHI
Shusuke YOSHIMOTO
Masahiko YOSHIMOTO
Hiroshi KAWAGUCHI

Publication
IEICE TRANSACTIONS on Electronics   Vol.E95-C    No.4    pp.579-585
Publication Date: 2012/04/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E95.C.579
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
SRAM,  FD-SOI,  Inter-die variation,  

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Summary: 
We propose a novel substrate-bias control scheme for an FD-SOI SRAM that suppresses inter-die variability. The proposed circuits detect inter-die threshold-voltage variation automatically, and then maximize read/write margins of memory cells to supply the substrate bias. We confirmed that a 486-kb 6T SRAM operates at 0.42 V, in which an FS corner can be compared as much as 0.14 V or more.