IEICE Trans

Tadashi NISHIMURA

Partially Depleted SOI Technology with Body-Tied Hybrid Trench Isolation for High-Speed System-On-a-Chip Application Yasuo YAMAGUCHI Takashi IPPOSHI Kimio UEDA Koichiro MASHIKO Shigeto MAEGAWA Masahide INUISHI Tadashi NISHIMURA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2001/12/01 Vol. E84-C No. 12 pp. 1735-1745 Type of Manuscript: Special Section PAPER (Special Issue on Integrated Systems with New Concepts) Category: Keyword: SOI, SOC, partially depleted, isolation,
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Circuit-Level Electrothermal Simulation of Electrostatic Discharge in Integrated Circuits Ken-ichiro SONODA Motoaki TANIZAWA Kiyoshi ISHIKAWA Norihiko KOTANI Tadashi NISHIMURA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2000/08/25 Vol. E83-C No. 8 pp. 1317-1323 Type of Manuscript: Special Section PAPER (Special Issue on 1999 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD'99)) Category: Circuit Applications Keyword: electrostatic discharge, electrothermal simulation, circuit simulation,
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3-D Topography and Impurity Integrated Process Simulator (3-D MIPS) and Its Applications Masato FUJINAGO Tatsuya KUNIKIYO Tetsuya UCHIDA Eiji TSUKUDA Kenichiro SONODA Katsumi EIKYU Kiyoshi ISHIKAWA Tadashi NISHIMURA Satoru KAWAZU
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1999/06/25 Vol. E82-C No. 6 pp. 848-861 Type of Manuscript: Special Section PAPER (Special Issue on TCAD for Semiconductor Industries) Category: Keyword: LSI fabrication, process simulator, topography, impurity diffusion, segregation, capacitance,
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2-Dimensional Simulation of FN Current Suppression Including Phonon Assisted Tunneling Model in Silicon Dioxide Katsumi EIKYU Kiyohiko SAKAKIBARA Kiyoshi ISHIKAWA Tadashi NISHIMURA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1999/06/25 Vol. E82-C No. 6 pp. 889-893 Type of Manuscript: Special Section PAPER (Special Issue on TCAD for Semiconductor Industries) Category: Keyword: neutral trap, phonon assisted tunneling, FN current, endurance characteristic,
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Analysis and Optimization of Floating Body Cell Operation for High-Speed SOI-DRAM Fukashi MORISHITA Yasuo YAMAGUCHI Takahisa EIMORI Toshiyuki OASHI Kazutami ARIMOTO Yasuo INOUE Tadashi NISHIMURA Michihiro YAMADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1999/03/25 Vol. E82-C No. 3 pp. 544-552 Type of Manuscript: Special Section PAPER (Special Issue on Ultra-High-Speed IC and LSI Technology) Category: Silicon Devices Keyword: SOI-DRAM, floating body, high speed, low power, data retention characteristics,
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Features of SOI DRAM's and their Potential for Low-Voltage and/or Giga-Bit Scale DRAM's Yasuo YAMAGUCHI Toshiyuki OASHI Takahisa EIMORI Toshiaki IWAMATSU Shouichi MITAMOTO Katsuhiro SUMA Takahiro TSURUDA Fukashi MORISHITA Masakazu HIROSE Hideto HIDAKA Kazutami ARIMOTO Kazuyasu FUJISHIMA Yasuo INOUE Tadashi NISHIMURA Hirokazu MIYOSHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/06/25 Vol. E79-C No. 6 pp. 772-780 Type of Manuscript: INVITED PAPER (Special Issue on ULSI Memory Technology) Category: Dynamic RAMs Keyword: SOL, SIMOX, DRAM, low-voltage operation,
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Low-Voltage Operation of a High-Resistivity Load SOI SRAM Cell by Reduced Back-Gate-Bias Effect Yasuo YAMAGUCHI Jun TAKAHASHI Takehisa YAMAGUCHI Tomohisa WADA Toshiaki IWAMATSU Hans-Oliver JOACHIM Yasuo INOUE Tadashi NISHIMURA Natsuro TSUBOUCHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1995/07/25 Vol. E78-C No. 7 pp. 812-817 Type of Manuscript: Special Section PAPER (Special Issue on LSI Memory Device, Circuit, Architecture and Application Technologies for Multimedia Age) Category: Keyword: SOI, SIMOX, SRAM, low-voltage operation, back-gate bias effect,
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Soft-Error Study of DRAMs with Retrograde Well Structure by New Evaluation Method Yoshikazu OHNO Hiroshi KIMURA Ken-ichiro SONODA Tadashi NISHIMURA Shin-ichi SATOH Hirokazu SAYAMA Shigenori HARA Mikio TAKAI Hirokazu MIYOSHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1994/03/25 Vol. E77-C No. 3 pp. 399-405 Type of Manuscript: Special Section PAPER (Special Issue on Quarter Micron Si Device and Process Technologies) Category: Device Technology Keyword: soft-error, DRAM, microprobe, proton, mapping,
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Two-Dimensional Device Simulation of 0.1 µm Thin-Film SOI MOSFET's Hans-Oliver JOACHIM Yasuo YAMAGUCHI Kiyoshi ISHIKAWA Norihiko KOTANI Tadashi NISHIMURA Katsuhiro TSUKAMOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1992/12/25 Vol. E75-C No. 12 pp. 1498-1505 Type of Manuscript: Special Section PAPER (Special Issue on SOI (Si on Insulator) Devices) Category: Deep Sub-micron SOI CMOS Keyword: thin-film SOI MOSFET's, miniaturized devices, device simulation,
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Hot-Carrier Reliability in Submicrometer Ultra-Thin SOI-MOSFET's Yasuo YAMAGUCHI Masahiro SHIMIZU Yasuo INOUE Tadashi NISHIMURA Katsuhiro TSUKAMOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1992/12/25 Vol. E75-C No. 12 pp. 1465-1470 Type of Manuscript: Special Section PAPER (Special Issue on SOI (Si on Insulator) Devices) Category: Hot Carrier Keyword: thin SOI, hot-carrier, SIMOX, gate-overlapped LDD,
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