IEICE Trans

Takashi IPPOSHI

Look-Ahead Dynamic Threshold Voltage Control Scheme for Improving Write Margin of SOI-7T-SRAM Masaaki IIJIMA Kayoko SETO Masahiro NUMA Akira TADA Takashi IPPOSHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/12/01 Vol. E90-A No. 12 pp. 2691-2694 Type of Manuscript: Special Section LETTER (Special Section on VLSI Design and CAD Algorithms) Category: Memory Design and Test Keyword: PD-SOI, body-bias, SRAM, low power design,
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A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI Fukashi MORISHITA Hideyuki NODA Isamu HAYASHI Takayuki GYOHTEN Mako OKAMOTO Takashi IPPOSHI Shigeto MAEGAWA Katsumi DOSAKA Kazutami ARIMOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/04/01 Vol. E90-C No. 4 pp. 765-771 Type of Manuscript: Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies) Category: Memory Keyword: SOI, capacitorless, DRAM, low power, data retention,
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Boosted Voltage Scheme with Active Body-Biasing Control on PD-SOI for Ultra Low Voltage Operation Masaaki IIJIMA Masayuki KITAMURA Masahiro NUMA Akira TADA Takashi IPPOSHI Shigeto MAEGAWA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/04/01 Vol. E90-C No. 4 pp. 666-674 Type of Manuscript: Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies) Category: Digital Keyword: low power design, PD-SOI, body-bias, pass-transistor logic, circuit simulation, SRAM,
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A Low-Power Microcontroller with Body-Tied SOI Technology Hisakazu SATO Yasuhiro NUNOMURA Niichi ITOH Koji NII Kanako YOSHIDA Hironobu ITO Jingo NAKANISHI Hidehiro TAKATA Yasunobu NAKASE Hiroshi MAKINO Akira YAMADA Takahiko ARAKAWA Toru SHIMIZU Yuichi HIRANO Takashi IPPOSHI Shuhei IWADE
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2004/04/01 Vol. E87-C No. 4 pp. 563-570 Type of Manuscript: Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies) Category: Keyword: low power, high speed, microcontroller, SOI,
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Partially Depleted SOI Technology with Body-Tied Hybrid Trench Isolation for High-Speed System-On-a-Chip Application Yasuo YAMAGUCHI Takashi IPPOSHI Kimio UEDA Koichiro MASHIKO Shigeto MAEGAWA Masahide INUISHI Tadashi NISHIMURA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2001/12/01 Vol. E84-C No. 12 pp. 1735-1745 Type of Manuscript: Special Section PAPER (Special Issue on Integrated Systems with New Concepts) Category: Keyword: SOI, SOC, partially depleted, isolation,
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A CAD-Compatible SOI-CMOS Gate Array Using 0.35µm Partially-Depleted Transistors Kimio UEDA Koji NII Yoshiki WADA Shigenobu MAEDA Toshiaki IWAMATSU Yasuo YAMAGUCHI Takashi IPPOSHI Shigeto MAEGAWA Koichiro MASHIKO Yasutaka HORIBA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2000/02/25 Vol. E83-C No. 2 pp. 205-211 Type of Manuscript: Special Section PAPER (Special Issue on Low-Power High-Speed CMOS LSI Technologies) Category: Keyword: SOI, CMOS, field-shield isolation, gate array, low-power, high-speed,
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Analysis of the Delay Distributions of 0.5 µm SOI LSIs Toshiaki IWAMATSU Takashi IPPOSHI Yasuo YAMAGUCHI Kimio UEDA Koichiro MASHIKO Shigeto MAEGAWA Yasuo INOUE Tadashi HIRAO Tdashi NISHIMURA Akihiko YASUOKA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1997/03/25 Vol. E80-C No. 3 pp. 464-471 Type of Manuscript: Special Section PAPER (Special Issue on SOI Devices and Their Process Technologies) Category: Keyword: SOI, SIMOX, divider, adder, high-speed, low voltage,
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