A 6.93-µm2 Full CMOS SRAM Cell Technology for 1.8-V High-Performance Cache Memory

Masataka MINAMI  Nagatoshi OHKI  Hiroshi ISHIDA  Toshiaki YAMANAKA  Akihiro SHIMIZU  Koichiro ISHIBASHI  Akira SATOH  Tokuo KURE  Takashi NISHIDA  Takahiro NAGANO  

IEICE TRANSACTIONS on Electronics   Vol.E80-C   No.4   pp.590-596
Publication Date: 1997/04/25
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Integrated Electronics
SRAM,  full CMOS cell,  local interconnect,  TiN,  

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A high-performance microprocessor-compatible small size full CMOS SRAM cell technology for under 1.8-V operation has been developed. Less than 1-µm spacing between the n and pMOSFETs is achieved by using a retrograde well combined with SSS-OSELO technology. To connect the gates of a driver nMOSFET and a load pMOSFET directly, a 0.3-µm n-gate load pMOSFET, formed by amorphous-Si-film through-channel implantation, is merged with a 0.25-µm p-gate pMOSFET for the peripheral circuits. The memory cell area is reduced by using a mask-free contact process for the local interconnect, which includes titanium-nitride wet-etching using a plasma-TEOS silicone-dioxide mask. The newly developed memory cell was demonstrated using 0.25-µm CMOS process technology. A 6.93-µm2 and 1-V operation full CMOS SRAM cell with a high-performance circuit was achieved by a simple fabrication process.