4-Port Unified Data/Instruction Cache Design with Distributed Crossbar and Interleaved Cache-Line Words

Koh JOHGUCHI  Hans Jurgen MATTAUSCH  Tetsushi KOIDE  Tetsuo HIRONAKA  

IEICE TRANSACTIONS on Electronics   Vol.E90-C   No.11   pp.2157-2160
Publication Date: 2007/11/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e90-c.11.2157
Print ISSN: 0916-8516
Type of Manuscript: LETTER
Category: Integrated Electronics
multi-port memory,  unified cache,  SRAM,  CMOS,  

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The presented unified data/instruction cache design uses multiple banks and features 4 ports, distributed crossbar, different word-length for data and instruction ports, interleaved cache-line words and synchronous access with hidden precharge. A 20.5 KByte storage capacity is integrated in 5-metal-layer CMOS logic technology with 200 nm minimum gate length and a 3.4 ns access-cycle time is achieved. The access bandwidth corresponds to 10 ports with standard word-length, while the cost in increased Si-area is only 25% in comparison to a 1-port cache.