A Low Power Data Storage Circuit with an Intermittent Power Supply Scheme for Sub-1 V MT-CMOS LSIs

Hironori AKAMATSU  Toru IWATA  Hiroyuki YAMAUCHI  Hisakazu KOTANI  Akira MATSUZAWA  Hiro YAMAMOTO  Takashi HIRATA  

IEICE TRANSACTIONS on Electronics   Vol.E80-C    No.12    pp.1572-1577
Publication Date: 1997/12/25
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Low-Power and High-Speed LSI Technologies)
multiple-threshold,  1-volt,  MT-CMOS,  data storage circuit,  SRAM,  virtual power line,  intermittent connection,  

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An experimental latch circuit is fabricated by using a 0.35µm MT-CMOS technology. This latch circuit has a volume smaller by 30%, a delay time shorter by 10%, and has an active power consumption smaller by 10% over those of a conventional MT-CMOS circuit. Furthermore, at a operation frequency of 100 MHz, an SRAM employing this IPS scheme has a standby current which is 0.4% of SRAM's without using IPS scheme.