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| Yusuke MATSUNAGA
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A Test Pattern Compaction Method Using SAT-Based Fault Grouping
Yusuke MATSUNAGA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/12/01
Vol. E99-A
No. 12
pp. 2302-2309
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category:
Keyword:
ATPG, SAT, test pattern, | | | Summary | Full Text:PDF | |
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Accelerating SAT-Based Boolean Matching for Heterogeneous FPGAs Using One-Hot Encoding and CEGAR Technique
Yusuke MATSUNAGA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/07/01
Vol. E99-A
No. 7
pp. 1374-1380
Type of Manuscript:
Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category:
Keyword:
logic synthesis, technology mapping, FPGA, SAT, | | | Summary | Full Text:PDF | |
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Synthesis Algorithm for Parallel Index Generator
Yusuke MATSUNAGA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/12/01
Vol. E97-A
No. 12
pp. 2451-2458
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword:
logic synthesis, index generation function, | | | Summary | Full Text:PDF | |
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Efficient Cut Enumeration Heuristics for Depth-Optimum Technology Mapping for LUT-Based FPGAs
Taiga TAKATA Yusuke MATSUNAGA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A
No. 12
pp. 3268-3275
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Embedded, Real-Time and Reconfigurable Systems
Keyword:
FPGA, technology mapping, cut enumeration, | | | Summary | Full Text:PDF | |
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FOREWORD
Yusuke MATSUNAGA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/12/01
Vol. E90-A
No. 12
pp. 2649-2650
Type of Manuscript:
FOREWORD
Category:
Keyword:
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Timing-Constrained Area Minimization Algorithm for Parallel Prefix Adders
Taeko MATSUNAGA Yusuke MATSUNAGA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/12/01
Vol. E90-A
No. 12
pp. 2770-2777
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis and Verification
Keyword:
parallel prefix adder, arithmetic synthesis, dynamic programming, | | | Summary | Full Text:PDF | |
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FOREWORD
Yusuke MATSUNAGA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/04/01
Vol. E90-A
No. 4
pp. 705-706
Type of Manuscript:
FOREWORD
Category:
Keyword:
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An Efficient Algorithm Finding Simple Disjoint Decompositions Using BDDs
Yusuke MATSUNAGA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/12/01
Vol. E85-A
No. 12
pp. 2715-2724
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword:
functional decomposition, BDDs, logic synthesis, FPGA, | | | Summary | Full Text:PDF | |
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