Keyword : binary decision diagrams


Exponential Lower Bounds on the Size of Variants of OBDD Representing Integer Division
Takashi HORIYAMA Shuzo YAJIMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/08/25
Vol. E81-D  No. 8 ; pp. 793-800
Type of Manuscript:  PAPER
Category: Algorithm and Computational Complexity
Keyword: 
Boolean functiondivisionbinary decision diagramslower boundfooling set
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A Variable Partitioning Algorithm of BDD for FPGA Technology Mapping
Jie-Hong JIANG Jing-Yang JOU Juinn-Dar HUANG Jung-Shian WEI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/10/25
Vol. E80-A  No. 10 ; pp. 1813-1819
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
binary decision diagramsequivalent classRoth-Karp decompositionLUT-based FPGA
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Generalized Reed-Muller Expressions: Complexity and an Exact Minimization Algorithm
Tsutomu SASAO Debatosh DEBNATH 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/12/25
Vol. E79-A  No. 12 ; pp. 2123-2130
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
AND-EXORReed-Muller expressioncomplexity of logic networkslogic minimizationbinary decision diagramseasily testable networks
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Phase Optimization in Technology Mapping
Yusuke MATSUNAGA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/12/25
Vol. E78-A  No. 12 ; pp. 1735-1741
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
logic synthesistechnology mappingphase optimizationbinary decision diagrams
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A New Method to Represent Sets of Products: Ternary Decision Diagrams
Koichi YASUOKA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/12/25
Vol. E78-A  No. 12 ; pp. 1722-1728
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
sum-of-products formringsum-products formlogic functionbinary decision diagrams
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A New Algorithm for Boolean Matching Utilizing Structural Information
Yusuke MATSUNAGA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/03/25
Vol. E78-D  No. 3 ; pp. 219-223
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: Logic Synthesis
Keyword: 
logic synthesistechnology mappingBoolean matchingbinary decision diagrams
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Symbolic Scheduling Techniques
Ivan P. RADIVOJEVI Forrest BREWER 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/03/25
Vol. E78-D  No. 3 ; pp. 224-230
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: High-Level Synthesis
Keyword: 
high level synthesisschedulingcomputer-aided designbinary decision diagrams
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Compaction of Test Sets for Combinational Circuits Based on Symbolic Fault Simulation
Hiroyuki HIGUCHI Nagisa ISHIURA Shuzo YAJIMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/09/25
Vol. E76-D  No. 9 ; pp. 1121-1127
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: Test
Keyword: 
test generationcombinational circuitscompact test setsbinary decision diagrams
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Synthesis of Multilevel Logic Circuits from Binary Decision Diagrams
Nagisa ISHIURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/09/25
Vol. E76-D  No. 9 ; pp. 1085-1092
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: Logic Synthesis
Keyword: 
logic synthesisbinary decision diagramscombinational circuits
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Analysis of the Trends in Logic Synthesis
Gabrièle SAUCIER 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/09/25
Vol. E76-D  No. 9 ; pp. 1006-1017
Type of Manuscript:  INVITED PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: Logic Synthesis
Keyword: 
logic synthesisalgebraic factorizationbinary decision diagrams
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Minimum-Width Method of Variable Ordering for Binary Decision Diagrams
Shin-ichi MINATO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/03/25
Vol. E75-A  No. 3 ; pp. 392-399
Type of Manuscript:  Special Section PAPER (Special Section on the 4th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
binary decision diagramsboolean functionlogic synthesisvariable ordering
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