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A Test Pattern Compaction Method Using SAT-Based Fault Grouping
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/12/01
Online ISSN: 1745-1337
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
ATPG, SAT, test pattern,
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This paper presents a test pattern compaction algorithm applicable for large scale circuits. The proposed methods formalizes the test pattern compaction problem as a problem finding minimum set of compatible fault groups. Also, an efficient algorithm checking compatibility of fault group is proposed. The experimental results show that the proposed algorithm achieves similar or better results against a couple of existing methods, especially for middle circuits.