Keyword : binary decision diagram


BDD-Constrained A* Search: A Fast Method for Solving Constrained Shortest-Path Problems
Fumito TAKEUCHI Masaaki NISHINO Norihito YASUDA Takuya AKIBA Shin-ichi MINATO Masaaki NAGATA 
Publication:   
Publication Date: 2017/12/01
Vol. E100-D  No. 12 ; pp. 2945-2952
Type of Manuscript:  PAPER
Category: Fundamentals of Information Systems
Keyword: 
DAG shortest pathbinary decision diagramcombinatorial optimizationA* search
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Computation of the Total Autocorrelation over Shared Binary Decision Diagrams
Miloš RADMANOVIC Radomir S. STANKOVIC Claudio MORAGA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/05/01
Vol. E97-A  No. 5 ; pp. 1140-1143
Type of Manuscript:  LETTER
Category: VLSI Design Technology and CAD
Keyword: 
switching theorycomputation of transformsbinary decision diagramBDD-package
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Reconfigurable Circuit Design Based on Arithmetic Logic Unit Using Double-Gate CNTFETs
Hiroshi NINOMIYA Manabu KOBAYASHI Yasuyuki MIURA Shigeyoshi WATANABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/02/01
Vol. E97-A  No. 2 ; pp. 675-678
Type of Manuscript:  LETTER
Category: VLSI Design Technology and CAD
Keyword: 
reconfigurable logic circuit designambipolar devicedouble-gate CNTFETbinary decision diagramarithmetic logic unit
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Reduced Reconfigurable Logic Circuit Design Based on Double Gate CNTFETs Using Ambipolar Binary Decision Diagram
Hiroshi NINOMIYA Manabu KOBAYASHI Shigeyoshi WATANABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/01/01
Vol. E96-A  No. 1 ; pp. 356-359
Type of Manuscript:  LETTER
Category: Circuit Theory
Keyword: 
reconfigurable logic designambipolar devicedouble gate CNTFETbinary decision diagram
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BDD Representation for Incompletely Specified Multiple-Output Logic Functions and Its Applications to the Design of LUT Cascades
Munehiro MATSUURA Tsutomu SASAO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/12/01
Vol. E90-A  No. 12 ; pp. 2762-2769
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis and Verification
Keyword: 
incompletely specified functioncharacteristic functionbinary decision diagramfunctional decompositionLUT cascade
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Single-Electron Logic Systems Based on a Graphical Representation of Digital Functions
Yoshihito AMEMIYA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/11/01
Vol. E89-C  No. 11 ; pp. 1504-1511
Type of Manuscript:  INVITED PAPER (Special Section on Novel Device Architectures and System Integration Technologies)
Category: 
Keyword: 
single electron circuitlogic gatebinary decision diagramquantum dotnanostructure
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An Algorithm for Generating Generic BDDs
Tetsushi KATAYAMA Hiroyuki OCHI Takao TSUDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A  No. 12 ; pp. 2505-2512
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
combinational synthesislogic functionswitching theorybinary decision diagrampass-transistor logic
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A Binding Algorithm for Retargetable Compilation to Non-orthogonal DSP Architectures
Masayuki YAMAGUCHI Nagisa ISHIURA Takashi KAMBE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A  No. 12 ; pp. 2630-2639
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Compiler
Keyword: 
retargetable compilerbindingnon-orthogonal architectureDSPbinary decision diagram
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On Properties of Kleene TDDs
Yukihiro IGUCHI Tsutomu SASAO Munehiro MATSUURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/07/25
Vol. E81-D  No. 7 ; pp. 716-723
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Diagnosis of VLSI)
Category: Logic Simulation and Logic Optimization
Keyword: 
binary decision diagramternary decision diagramlogic simulationternary logic
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Single-Electron Logic Systems Based on the Binary Decision Diagram
Noboru ASAHI Masamichi AKAZAWA Yoshihito AMEMIYA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/01/25
Vol. E81-C  No. 1 ; pp. 49-56
Type of Manuscript:  Special Section PAPER (Special Issue on Technology Challenges for Single Electron Devices)
Category: 
Keyword: 
binary decision diagramBDDsingle electronlogic circuitaddercomparator
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Formal Verification of Totally Self-Checking Properties of Combinational Circuits
Kazuo KAWAKUBO Koji TANAKA Hiromi HIRAISHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1997/01/25
Vol. E80-D  No. 1 ; pp. 57-62
Type of Manuscript:  Special Section PAPER (Special Issue on Fault-Tolerant Computing)
Category: Verification
Keyword: 
formal verificationtotally self-checkingfault tolerancebinary decision diagram
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Formal Design Verification of Combinational Circuits Specified by Recurrence Equations
Hiroyuki OCHI Shuzo YAJIMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/10/25
Vol. E79-D  No. 10 ; pp. 1431-1435
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: Design Verification
Keyword: 
formal design verificationbinary decision diagramarithmetic circuitsspecificationrecurrence equations
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Implicit Representations of Graphs by OBDDs and Patricia BDDs
Mizuho IWAIHARA Masanori HIROFUJI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/07/25
Vol. E79-A  No. 7 ; pp. 1068-1078
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
binary decision diagramdata structureformal verificationgraph representationBDD size
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Datapath Scheduling for Behavioral Description with Conditional Branches
Akihisa YAMADA Toshiki YAMAZAKI Nagisa ISHIURA Isao SHIRAKAWA Takashi KAMBE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/12/25
Vol. E77-A  No. 12 ; pp. 1999-2009
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
high-level synthesisdatapath scheduling0-1 integer programming problembinary decision diagrambranch-and-bound method
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Computational Complexity of Manipulating Binary Decision Diagrams
Yasuhiko TAKENAGA Shuzo YAJIMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1994/06/25
Vol. E77-D  No. 6 ; pp. 642-647
Type of Manuscript:  PAPER
Category: Algorithm and Computational Complexity
Keyword: 
binary decision diagramcomputatioal complexityBoolean functionparallel algorithm
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On the Computational Power of Binary Decision Diagrams
Hiroshi SAWADA Yasuhiko TAKENAGA Shuzo YAJIMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1994/06/25
Vol. E77-D  No. 6 ; pp. 611-618
Type of Manuscript:  PAPER
Category: Automata, Languages and Theory of Computing
Keyword: 
binary decision diagramon-line Turing machineplaner circuitpermutationcomplete language
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Pattern Generation for Locating Logic Design Errors
Masahiro TOMITA Naoaki SUGANUMA Kotaro HIRANO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/05/25
Vol. E77-A  No. 5 ; pp. 881-893
Type of Manuscript:  PAPER
Category: Computer Aided Design (CAD)
Keyword: 
binary decision diagrampattern generationlogic diagnosisrectificationlogic verification
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MINT--An Exact Algorithm for Finding Minimum Test Set--
Yusuke MATSUNAGA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/10/25
Vol. E76-A  No. 10 ; pp. 1652-1658
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
test pattern generationminimum test setbinary decision diagramminimum set covering problem
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Optimization of Pseudo-Kronecker Expressions Using Multiple-Place Decision Diagrams
Tsutomu SASAO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/05/25
Vol. E76-D  No. 5 ; pp. 562-570
Type of Manuscript:  Special Section PAPER (Special Issue on Multiple-Valued Logic)
Category: Logic Design
Keyword: 
Reed-Muller expressionAND-EXOR expressionlogic minimizationbinary decision diagramsymmetric functions
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Parallel Binary Decision Diagram Manipulation
Shinji KIMURA Tsutomu IGAKI Hiromasa HANEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/10/25
Vol. E75-A  No. 10 ; pp. 1255-1262
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
binary decision diagramparallel algorithmlogic verification
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Formal Design Verification of Sequential Machines Based on Symbolic Model Checking for Branching Time Regular Temporal Logic
Kiyoharu HAMAGUCHI Hiromi HIRAISHI Shuzo YAJIMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/10/25
Vol. E75-A  No. 10 ; pp. 1220-1229
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
design verificationsequential machinestemporal logicmodel checkingbinary decision diagram
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