IEICE Trans

Kazuaki MURAKAMI

A Reconfigurable Data-Path Accelerator Based on Single Flux Quantum Circuits Hiroshi KATAOKA Hiroaki HONDA Farhad MEHDIPOUR Nobuyuki YOSHIKAWA Akira FUJIMAKI Hiroyuki AKAIKE Naofumi TAKAGI Kazuaki MURAKAMI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2014/03/01 Vol. E97-C No. 3 pp. 141-148 Type of Manuscript: INVITED PAPER (Special Section on Leading-Edge Technology of Superconductor Large-Scale Integrated Circuits) Category: Keyword: single flux quantum, reconfigurable data-path, accelerator,
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Optimisations Techniques for the Automatic ISA Customisation Algorithm Antoine TROUVE Kazuaki MURAKAMI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2012/02/01 Vol. E95-D No. 2 pp. 437-440 Type of Manuscript: Special Section LETTER (Special Section on Reconfigurable Systems) Category: Design Optimisation Keyword: reconfigurable computing, custom instruction generation, optimisation,
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NSIM: An Interconnection Network Simulator for Extreme-Scale Parallel Computers Hideki MIWA Ryutaro SUSUKITA Hidetomo SHIBAMURA Tomoya HIRAO Jun MAKI Makoto YOSHIDA Takayuki KANDO Yuichiro AJIMA Ikuo MIYOSHI Toshiyuki SHIMIZU Yuji OINAGA Hisashige ANDO Yuichi INADOMI Koji INOUE Mutsumi AOYAGI Kazuaki MURAKAMI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2011/12/01 Vol. E94-D No. 12 pp. 2298-2308 Type of Manuscript: Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking) Category: Keyword: discrete event simulation, multiprocessor interconnection, parallel processing,
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Rapid Design Space Exploration of a Reconfigurable Instruction-Set Processor Farhad MEHDIPOUR Hamid NOORI Koji INOUE Kazuaki MURAKAMI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/12/01 Vol. E92-A No. 12 pp. 3182-3192 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Embedded, Real-Time and Reconfigurable Systems Keyword: reconfigurable instruction-set processor, analytical modeling, design space exploration, data flow graph accelerator,
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Identifying Processor Bottlenecks in Virtual Machine Based Execution of Java Bytecode Pradeep RAO Kazuaki MURAKAMI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2009/10/01 Vol. E92-C No. 10 pp. 1265-1275 Type of Manuscript: Special Section PAPER (Special Section on Hardware and Software Technologies on Advanced Microprocessors) Category: Keyword: processor microarchitecture, Java virtual machine, performance bottlenecks, empirical models,
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Reducing On-Chip DRAM Energy via Data Transfer Size Optimization Takatsugu ONO Koji INOUE Kazuaki MURAKAMI Kenji YOSHIDA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2009/04/01 Vol. E92-C No. 4 pp. 433-443 Type of Manuscript: Special Section PAPER (Special Section on Low-Leakage, Low-Voltage, Low-Power and High-Speed Technologies for System LSIs in Deep-Submicron Era) Category: Keyword: low power, variable line-size, on-chip DRAM, high bandwidth, embedded systems,
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Character Projection Mask Set Optimization for Enhancing Throughput of MCC Projection Systems Makoto SUGIHARA Yusuke MATSUNAGA Kazuaki MURAKAMI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/12/01 Vol. E91-A No. 12 pp. 3451-3460 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Physical Level Design Keyword: maskless lithography, multi-column-cells, character projection, variable-shaped beam, throughput,
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Performance Models for MPI Collective Communications with Network Contention Hyacinthe NZIGOU MAMADOU Takeshi NANRI Kazuaki MURAKAMI
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2008/04/01 Vol. E91-B No. 4 pp. 1015-1024 Type of Manuscript: PAPER Category: Network Keyword: MPI, collective communications, performance prediction, queuing theory, contention issue,
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Temperature-Aware Configurable Cache to Reduce Energy in Embedded Systems Hamid NOORI Maziar GOUDARZI Koji INOUE Kazuaki MURAKAMI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2008/04/01 Vol. E91-C No. 4 pp. 418-431 Type of Manuscript: Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories) Category: Keyword: temperature-aware design, cache memory, leakage current, low energy, embedded systems,
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A Reconfigurable Functional Unit with Conditional Execution for Multi-Exit Custom Instructions Hamid NOORI Farhad MEHDIPOUR Koji INOUE Kazuaki MURAKAMI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2008/04/01 Vol. E91-C No. 4 pp. 497-508 Type of Manuscript: Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories) Category: Keyword: custom instructions, extensible processor, reconfigurable functional unit, conditional execution,
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Reliable Cache Architectures and Task Scheduling for Multiprocessor Systems Makoto SUGIHARA Tohru ISHIHARA Kazuaki MURAKAMI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2008/04/01 Vol. E91-C No. 4 pp. 410-417 Type of Manuscript: Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories) Category: Keyword: single event upset, SRAM, DRAM, reliability, cache architecture, task scheduling,
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Proposal of a Desk-Side Supercomputer with Reconfigurable Data-Paths Using Rapid Single-Flux-Quantum Circuits Naofumi TAKAGI Kazuaki MURAKAMI Akira FUJIMAKI Nobuyuki YOSHIKAWA Koji INOUE Hiroaki HONDA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2008/03/01 Vol. E91-C No. 3 pp. 350-355 Type of Manuscript: INVITED PAPER (Special Section on Recent Progress in Superconductive Digital Electronics) Category: Keyword: superconductor, rapid single-flux-quantum circuit, reconfigurable data-path, high-performance computing, supercomputer,
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Improving Performance and Energy Saving in a Reconfigurable Processor via Accelerating Control Data Flow Graphs Farhad MEHDIPOUR Hamid NOORI Morteza SAHEB ZAMANI Koji INOUE Kazuaki MURAKAMI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2007/12/01 Vol. E90-D No. 12 pp. 1956-1966 Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems) Category: Reconfigurable Device and Design Tools Keyword: reconfigurable accelerator, conditional execution, control data flow graph, temporal partitioning, reconfigurable processor,
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Architectural-Level Soft-Error Modeling for Estimating Reliability of Computer Systems Makoto SUGIHARA Tohru ISHIHARA Kazuaki MURAKAMI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/10/01 Vol. E90-C No. 10 pp. 1983-1991 Type of Manuscript: Special Section PAPER (Special Section on VLSI Technology toward Frontiers of New Market) Category: VLSI Design Technology Keyword: soft error, reliability, estimation, computer systems, instruction-set simulation,
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A Next-Generation Enterprise Server System with Advanced Cache Coherence Chips Mariko SAKAMOTO Akira KATSUNO Go SUGIZAKI Toshio YOSHIDA Aiichiro INOUE Koji INOUE Kazuaki MURAKAMI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/10/01 Vol. E90-C No. 10 pp. 1972-1982 Type of Manuscript: Special Section PAPER (Special Section on VLSI Technology toward Frontiers of New Market) Category: VLSI Architecture for Communication/Server Systems Keyword: enterprise server system, cache coherence, distributed shared memory, online transaction processing, performance evaluation,
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Technology Mapping Technique for Increasing Throughput of Character Projection Lithography Makoto SUGIHARA Kenta NAKAMURA Yusuke MATSUNAGA Kazuaki MURAKAMI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/05/01 Vol. E90-C No. 5 pp. 1012-1020 Type of Manuscript: Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices) Category: Lithography-Related Techniques Keyword: maskless lithography, character projection, variable-shaped beam, technology mapping, throughput,
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Cell Library Development Methodology for Throughput Enhancement of Character Projection Equipment Makoto SUGIHARA Taiga TAKATA Kenta NAKAMURA Ryoichi INANAMI Hiroaki HAYASHI Katsumi KISHIMOTO Tetsuya HASEBE Yukihiro KAWANO Yusuke MATSUNAGA Kazuaki MURAKAMI Katsuya OKUMURA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/03/01 Vol. E89-C No. 3 pp. 377-383 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era) Category: CAD Keyword: cell library, character projection, electron beam, EB shots, throughput, optimization, integer linear programming,
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Quantitative Evaluation of State-Preserving Leakage Reduction Algorithm for L1 Data Caches Reiko KOMIYA Koji INOUE Vasily G. MOSHNYAGA Kazuaki MURAKAMI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/04/01 Vol. E88-A No. 4 pp. 862-868 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: low power, cache, leakage,
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Test Architecture Optimization for System-on-a-Chip under Floorplanning Constraints Makoto SUGIHARA Kazuaki MURAKAMI Yusuke MATSUNAGA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/12/01 Vol. E87-A No. 12 pp. 3174-3184 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Test Keyword: core-based design, SOC, TAM, test architecture, floorplan, test scheduling,
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Evaluating Online Hot Instruction Sequence Profilers for Dynamically Reconfigurable Functional Units Takanori HAYASHIDA Kazuaki MURAKAMI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2003/05/01 Vol. E86-D No. 5 pp. 901-909 Type of Manuscript: Special Section PAPER (Special Issue on Reconfigurable Computing) Category: Keyword: online profiling, dynamically reconfigurable computing, hardware profiling,
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Relaxing Constraints due to Data and Control Dependences Katsuhiko METSUGI Kazuaki MURAKAMI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2003/05/01 Vol. E86-D No. 5 pp. 920-928 Type of Manuscript: PAPER Category: Computer Systems Keyword: TLSP, ILP, data dependence, control dependence, value prediction,
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Instruction Encoding for Reducing Power Consumption of I-ROMs Based on Execution Locality Koji INOUE Vasily G. MOSHNYAGA Kazuaki MURAKAMI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/04/01 Vol. E86-A No. 4 pp. 799-805 Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 15th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: low power, instruction ROM, embedded systems, encoding,
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Omitting Cache Look-up for High-Performance, Low-Power Microprocessors Koji INOUE Vasily G. MOSHNYAGA Kazuaki MURAKAMI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2002/02/01 Vol. E85-C No. 2 pp. 279-287 Type of Manuscript: Special Section PAPER (Special Issue on High-Performance and Low-Power Microprocessors) Category: Low-Power Technologies Keyword: cache, low power, look up, run time,
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Trends in High-Performance, Low-Power Cache Memory Architectures Koji INOUE Vasily G. MOSHNYAGA Kazuaki MURAKAMI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2002/02/01 Vol. E85-C No. 2 pp. 304-314 Type of Manuscript: Special Section PAPER (Special Issue on High-Performance and Low-Power Microprocessors) Category: High-Performance Technologies Keyword: cache, low power, high performance, microprocessor, survey,
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Trends in High-Performance, Low-Power Processor Architectures Kazuaki MURAKAMI Hidetaka MAGOSHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2001/02/01 Vol. E84-C No. 2 pp. 131-138 Type of Manuscript: Special Section PAPER (Special Issue on Low-Power High-Performance VLSI Processors and Technologies) Category: Keyword: processor architecture, high performance design, low power design,
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A High-Performance/Low-Power On-Chip Memory-Path Architecture with Variable Cache-Line Size Koji INOUE Koji KAI Kazuaki MURAKAMI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2000/11/25 Vol. E83-C No. 11 pp. 1716-1723 Type of Manuscript: Special Section PAPER (Special Issue on Low-power LSIs and Technologies) Category: Keyword: cache, low power, variable line-size, merged DRAM/logic LSIs, high bandwidth,
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Dynamically Variable Line-Size Cache Architecture for Merged DRAM/Logic LSIs Koji INOUE Koji KAI Kazuaki MURAKAMI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2000/05/25 Vol. E83-D No. 5 pp. 1048-1057 Type of Manuscript: PAPER Category: Computer System Element Keyword: cache, variable line-size, merged DRAM/logic LSIs, high bandwidth,
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A High-Performance and Low-Power Cache Architecture with Speculative Way-Selection Koji INOUE Tohru ISHIHARA Kazuaki MURAKAMI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2000/02/25 Vol. E83-C No. 2 pp. 186-194 Type of Manuscript: Special Section PAPER (Special Issue on Low-Power High-Speed CMOS LSI Technologies) Category: Keyword: cache, low power, low energy, way prediction, high performance,
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FOREWORD Kazuaki MURAKAMI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1998/09/25 Vol. E81-C No. 9 pp. 1373-1373 Type of Manuscript: FOREWORD Category: Keyword:
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Evaluating DRAM Refresh Architectures for Merged DRAM/Logic LSIs Taku OHSAWA Koji KAI Kazuaki MURAKAMI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1998/09/25 Vol. E81-C No. 9 pp. 1455-1462 Type of Manuscript: Special Section PAPER (Special Issue on Novel VLSI Processor Architectures) Category: Keyword: DRAM, DRAM refresh, merged DRAM/logic, system LSI, low power,
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Analyzing and Reducing the Impact of Shorter Data Retention Time on the Performance of Merged DRAM/Logic LSIs Koji KAI Akihiko INOUE Taku OHSAWA Kazuaki MURAKAMI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1998/09/25 Vol. E81-C No. 9 pp. 1448-1454 Type of Manuscript: Special Section PAPER (Special Issue on Novel VLSI Processor Architectures) Category: Keyword: merged DRAM/logic LSIs, data retention time, refresh, yield,
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High Bandwidth, Variable Line-Size Cache Architecture for Merged DRAM/Logic LSIs Koji INOUE Koji KAI Kazuaki MURAKAMI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1998/09/25 Vol. E81-C No. 9 pp. 1438-1447 Type of Manuscript: Special Section PAPER (Special Issue on Novel VLSI Processor Architectures) Category: Keyword: cache, merged DRAM/logic LSIs, memory system,
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Tradeoffs in Processor Design for Superscalar Architectures Kazuaki MURAKAMI Morihiro KUGA Oubong GWUN Shinji TOMITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1991/11/25 Vol. E74-D No. 11 pp. 3883-3893 Type of Manuscript: PAPER Category: Computer Systems Keyword:
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