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Quantitative Evaluation of State-Preserving Leakage Reduction Algorithm for L1 Data Caches Reiko KOMIYA Koji INOUE Vasily G. MOSHNYAGA Kazuaki MURAKAMI | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/04/01
Vol. E88-A
No. 4
pp. 862-868
Type of Manuscript:
Special Section PAPER (Special Section on Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: low power, cache, leakage, | | Summary | Full Text:PDF | |
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Instruction Encoding for Reducing Power Consumption of I-ROMs Based on Execution Locality Koji INOUE Vasily G. MOSHNYAGA Kazuaki MURAKAMI | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/04/01
Vol. E86-A
No. 4
pp. 799-805
Type of Manuscript:
Special Section PAPER (Special Section of Selected Papers from the 15th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: low power, instruction ROM, embedded systems, encoding, | | Summary | Full Text:PDF | |
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Omitting Cache Look-up for High-Performance, Low-Power Microprocessors Koji INOUE Vasily G. MOSHNYAGA Kazuaki MURAKAMI | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2002/02/01
Vol. E85-C
No. 2
pp. 279-287
Type of Manuscript:
Special Section PAPER (Special Issue on High-Performance and Low-Power Microprocessors) Category: Low-Power Technologies Keyword: cache, low power, look up, run time, | | Summary | Full Text:PDF | |
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FOREWORD Kazuaki MURAKAMI | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1998/09/25
Vol. E81-C
No. 9
pp. 1373-1373
Type of Manuscript:
FOREWORD Category: Keyword:
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High Bandwidth, Variable Line-Size Cache Architecture for Merged DRAM/Logic LSIs Koji INOUE Koji KAI Kazuaki MURAKAMI | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1998/09/25
Vol. E81-C
No. 9
pp. 1438-1447
Type of Manuscript:
Special Section PAPER (Special Issue on Novel VLSI Processor Architectures) Category: Keyword: cache, merged DRAM/logic LSIs, memory system, | | Summary | Full Text:PDF | |
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Tradeoffs in Processor Design for Superscalar Architectures Kazuaki MURAKAMI Morihiro KUGA Oubong GWUN Shinji TOMITA | Publication: IEICE TRANSACTIONS on Information and Systems
Publication Date: 1991/11/25
Vol. E74-D
No. 11
pp. 3883-3893
Type of Manuscript:
PAPER Category: Computer Systems Keyword:
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