Enhanced Unique Sensitization for Efficient Test Generation

Yusuke MATSUNAGA  Masahiro FUJITA  

Publication
IEICE TRANSACTIONS on Information and Systems   Vol.E76-D   No.9   pp.1114-1120
Publication Date: 1993/09/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8532
Type of Manuscript: Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: Test
Keyword: 
computer hardware and disign,  testing and verification,  

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Summary: 
Test pattern generation is getting much harder as the circuit size becomes larger. One problem is that it tends to take much time and another one is that it is difficult to detect redundant faults. Aiming to cope with these problem, an enhanced unique sensitization technique is proposed in this paper. This powerful global implication reduces the number of backtracks with reasonable computational time. And a fast test pattern generator featuring this unique sensitization demonstrates its performance using large benchmark circuits with over ten thousands of gates. It takes only a minute to detect all testable faults and to identify all redundant faults of 20,000 gates circuit on a workstation.