Keyword : arithmetic synthesis

An Exact Approach for GPC-Based Compressor Tree Synthesis
Taeko MATSUNAGA Shinji KIMURA Yusuke MATSUNAGA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/12/01
Vol. E96-A  No. 12 ; pp. 2553-2560
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
compressor tree, generalized parallel counter, integer linear programming, arithmetic synthesis, 
 Summary | Full Text:PDF
Multi-Operand Adder Synthesis Targeting FPGAs
Taeko MATSUNAGA Shinji KIMURA Yusuke MATSUNAGA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A  No. 12 ; pp. 2579-2586
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
multi-operand adder, generalized parallel counter, arithmetic synthesis, FPGA, 
 Summary | Full Text:PDF
Timing-Constrained Area Minimization Algorithm for Parallel Prefix Adders
Taeko MATSUNAGA Yusuke MATSUNAGA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/12/01
Vol. E90-A  No. 12 ; pp. 2770-2777
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis and Verification
Keyword: 
parallel prefix adder, arithmetic synthesis, dynamic programming, 
 Summary | Full Text:PDF