Optimization of Sequential Synchronous Digital Circuits Using Structural Models Giovanni De MICHELI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1993/09/25 Vol. E76-DNo. 9 ;
pp. 1018-1029 Type of Manuscript: INVITED PAPER (Special Issue on Synthesis and Verification of Hardware Design) Category: Logic Synthesis Keyword: computer hardware and disign, synchronous circuits, CAD, logic synthesis,
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1993/09/25 Vol. E76-DNo. 9 ;
pp. 1114-1120 Type of Manuscript: Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design) Category: Test Keyword: computer hardware and disign, testing and verification,
