Keyword : test scheduling


Flexible Test Scheduling for an Asynchronous On-Chip Interconnect through Special Data Transfer
Tsuyoshi IWAGAKI Eiri TAKEDA Mineo KANEKO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A  No. 12 ; pp. 2563-2570
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
asynchronous on-chip interconnectCHAINstuck-at faulttest schedulinginteger linear programming
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Thermal-Aware Test Access Mechanism and Wrapper Design Optimization for System-on-Chips
Thomas Edison YU Tomokazu YONEDA Krishnendu CHAKRABARTY Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/10/01
Vol. E91-D  No. 10 ; pp. 2440-2448
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
SoC testingtest architecture designtest schedulingthermal constraint
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Test Scheduling for Multi-Clock Domain SoCs under Power Constraint
Tomokazu YONEDA Kimihiko MASUDA Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/03/01
Vol. E91-D  No. 3 ; pp. 747-755
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSIs)
Category: High-Level Testing
Keyword: 
multi-clock domain SoCtest schedulingtest access mechanismpower consumption
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Effective Domain Partitioning for Multi-Clock Domain IP Core Wrapper Design under Power Constraints
Thomas Edison YU Tomokazu YONEDA Danella ZHAO Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/03/01
Vol. E91-D  No. 3 ; pp. 807-814
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
multi-clock domainwrapper designSoCembedded core testtest scheduling
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A Memory Grouping Method for Reducing Memory BIST Logic of System-on-Chips
Masahide MIYAZAKI Tomokazu YONEDA Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2006/04/01
Vol. E89-D  No. 4 ; pp. 1490-1497
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
SoCtest schedulingwrapperdesign for testmemory BIST
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Power-Constrained Test Synthesis and Scheduling Algorithms for Non-Scan BIST-able RTL Data Paths
Zhiqiang YOU Ken'ichi YAMAGUCHI Michiko INOUE Jacob SAVIR Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/08/01
Vol. E88-D  No. 8 ; pp. 1940-1947
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
design for testabilityRTL data pathbuilt-in self-testlow power testingtest scheduling
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Test Architecture Optimization for System-on-a-Chip under Floorplanning Constraints
Makoto SUGIHARA Kazuaki MURAKAMI Yusuke MATSUNAGA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12 ; pp. 3174-3184
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Test
Keyword: 
core-based designSOCTAMtest architecturefloorplantest scheduling
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A DFT Selection Method for Reducing Test Application Time of System-on-Chips
Masahide MIYAZAKI Toshinori HOSOKAWA Hiroshi DATE Michiaki MURAOKA Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/03/01
Vol. E87-D  No. 3 ; pp. 609-619
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSI)
Category: SoC Testing
Keyword: 
test schedulingtest access mechanismwrapperdesign for test
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Preemptive System-on-Chip Test Scheduling
Erik LARSSON Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/03/01
Vol. E87-D  No. 3 ; pp. 620-629
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSI)
Category: SoC Testing
Keyword: 
test schedulingtest access mechanism designpreemptive schedulingsystem-on-chip testing
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Optimization of Test Accesses with a Combined BIST and External Test Scheme
Makoto SUGIHARA Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11 ; pp. 2731-2738
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Test
Keyword: 
test timeBISTexternal testCBETtest schedulingtest accesstest busexternal pins
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