Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/12/01 Vol. E94-ANo. 12 ;
pp. 2563-2570 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verification Keyword: asynchronous on-chip interconnect, CHAIN, stuck-at fault, test scheduling, integer linear programming,
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2008/03/01 Vol. E91-DNo. 3 ;
pp. 747-755 Type of Manuscript: Special Section PAPER (Special Section on Test and Verification of VLSIs) Category: High-Level Testing Keyword: multi-clock domain SoC, test scheduling, test access mechanism, power consumption,
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2006/04/01 Vol. E89-DNo. 4 ;
pp. 1490-1497 Type of Manuscript: PAPER Category: Dependable Computing Keyword: SoC, test scheduling, wrapper, design for test, memory BIST,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/12/01 Vol. E87-ANo. 12 ;
pp. 3174-3184 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Test Keyword: core-based design, SOC, TAM, test architecture, floorplan, test scheduling,
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2004/03/01 Vol. E87-DNo. 3 ;
pp. 609-619 Type of Manuscript: Special Section PAPER (Special Section on Test and Verification of VLSI) Category: SoC Testing Keyword: test scheduling, test access mechanism, wrapper, design for test,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/11/01 Vol. E84-ANo. 11 ;
pp. 2731-2738 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Test Keyword: test time, BIST, external test, CBET, test scheduling, test access, test bus, external pins,