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FOREWORD Mineo KANEKO | Publication:
Publication Date: 2018/07/01
Vol. E101-A
No. 7
pp. 1000-1001
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FOREWORD Mineo KANEKO | Publication:
Publication Date: 2017/12/01
Vol. E100-A
No. 12
pp. 2740-2740
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A Formal Approach to Optimal Register Binding with Ordered Clocking for Clock-Skew Tolerant Datapaths Keisuke INOUE Mineo KANEKO | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A
No. 12
pp. 2330-2337
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Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verification Keyword: clock-skew, ordered clocking, high-level synthesis, | | Summary | Full Text:PDF | |
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Simultaneous Optimization of Skew and Control Step Assignments in RT-Datapath Synthesis Takayuki OBATA Mineo KANEKO | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A
No. 12
pp. 3585-3595
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Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: high level synthesis, RT datapath, skew, wiring delay, scheduling, | | Summary | Full Text:PDF | |
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Characterization and Computation of Steiner Routing Based on Elmore's Delay Model Satoshi TAYU Mineo KANEKO | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/12/01
Vol. E85-A
No. 12
pp. 2764-2774
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Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Timing Analysis Keyword: Elmore's delay, Steiner tree, net, binary tree, Manhattan distance, | | Summary | Full Text:PDF | |
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Checking Scheme for ABFT Systems Based on Modified PD Graph under an Error Generation/Propagation Model Choon-Sik PARK Mineo KANEKO | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/06/25
Vol. E82-A
No. 6
pp. 1002-1008
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Special Section PAPER (Special Section of Papers Selected from 1998 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC '98)) Category: Keyword: fault tolerance, processor-data graph, checking scheme, error model, fault detection, fault location, | | Summary | Full Text:PDF | |
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Two-Dimensional Quadrilateral Recursive Digital Filters with Parallel Structure--Synthesis and Parallel Processing-- Tsuyoshi ISSHIKI Hiroaki KUNIEDA Mineo KANEKO | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/03/25
Vol. E75-A
No. 3
pp. 352-361
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Special Section PAPER (Special Section on the 4th Karuizawa Workshop on Circuits and Systems) Category: Keyword: quadrilateral recursive filters, parallel processing, | | Summary | Full Text:PDF | |
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MMAPC: An Effective Mixed-Mode Circuit Simulator Using Dynamic Circuit Partition Process Ben CHEN Mahoki ONODA Mineo KANEKO | Publication: IEICE TRANSACTIONS (1976-1990)
Publication Date: 1988/04/25
Vol. E71-E
No. 4
pp. 388-393
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PAPER Category: VLSI Design Technology Keyword:
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