IEICE Trans

Mineo KANEKO

High Level Congestion Detection from C/C++ Source Code for High Level Synthesis Masato TATSUOKA Mineo KANEKO
Publication: Publication Date: 2020/12/01 Vol. E103-A No. 12 pp. 1437-1446 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: wire congestion, high level synthesis, source code compiler, LLVM,
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FOREWORD Mineo KANEKO
Publication: Publication Date: 2018/07/01 Vol. E101-A No. 7 pp. 1000-1001 Type of Manuscript: FOREWORD Category: Keyword:
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FOREWORD Mineo KANEKO
Publication: Publication Date: 2017/12/01 Vol. E100-A No. 12 pp. 2740-2740 Type of Manuscript: FOREWORD Category: Keyword:
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Latency-Aware Selection of Check Variables for Soft-Error Tolerant Datapath Synthesis Junghoon OH Mineo KANEKO
Publication: Publication Date: 2017/07/01 Vol. E100-A No. 7 pp. 1506-1510 Type of Manuscript: Special Section LETTER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: check variable selection, cone-partitioning, speculative resource sharing, soft-error tolerant datapath, triple algorithm redundancy,
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Area-Efficient Soft-Error Tolerant Datapath Synthesis Based on Speculative Resource Sharing Junghoon OH Mineo KANEKO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2016/07/01 Vol. E99-A No. 7 pp. 1311-1322 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: speculative resource sharing, soft-error, fault tolerant datapath, triple algorithm redundancy, high-level synthesis, integer linear programming,
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Dual-Edge-Triggered Flip-Flop-Based High-Level Synthesis with Programmable Duty Cycle Keisuke INOUE Mineo KANEKO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2013/12/01 Vol. E96-A No. 12 pp. 2689-2697 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: dual-edge-triggered flip-flop, programmable duty cycle, operation scheduling, MILP, high-level synthesis,
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Heuristic and Exact Resource Binding Algorithms for Storage Optimization Using Flip-Flops and Latches Keisuke INOUE Mineo KANEKO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2013/08/01 Vol. E96-A No. 8 pp. 1712-1722 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: flip-flop/latch-based design, high-level synthesis, resource binding, storage-type selection,
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A Formal Approach to Optimal Register Binding with Ordered Clocking for Clock-Skew Tolerant Datapaths Keisuke INOUE Mineo KANEKO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2012/12/01 Vol. E95-A No. 12 pp. 2330-2337 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verification Keyword: clock-skew, ordered clocking, high-level synthesis,
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Flexible Test Scheduling for an Asynchronous On-Chip Interconnect through Special Data Transfer Tsuyoshi IWAGAKI Eiri TAKEDA Mineo KANEKO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/12/01 Vol. E94-A No. 12 pp. 2563-2570 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verification Keyword: asynchronous on-chip interconnect, CHAIN, stuck-at fault, test scheduling, integer linear programming,
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Backward-Data-Direction Clocking and Relevant Optimal Register Assignment in Datapath Synthesis Keisuke INOUE Mineo KANEKO Tsuyoshi IWAGAKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/04/01 Vol. E94-A No. 4 pp. 1067-1081 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: datapath synthesis, delay variation, register assignment, hold timing constraint, backward-data-direction clocking, integer linear programming,
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Optimal Register Assignment with Minimum-Path Delay Compensation for Variation-Aware Datapaths Keisuke INOUE Mineo KANEKO Tsuyoshi IWAGAKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/04/01 Vol. E92-A No. 4 pp. 1096-1105 Type of Manuscript: Special Section PAPER (Special Section on Advanced Technologies Emerging Mainly from the 21st Workshop on Circuits and Systems in Karuizawa) Category: Keyword: datapath synthesis, delay variation, register assignment, setup and hold constraints, minimum delay compensation, integer linear programming,
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Simultaneous Optimization of Skew and Control Step Assignments in RT-Datapath Synthesis Takayuki OBATA Mineo KANEKO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/12/01 Vol. E91-A No. 12 pp. 3585-3595 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: high level synthesis, RT datapath, skew, wiring delay, scheduling,
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Novel Register Sharing in Datapath for Structural Robustness against Delay Variation Keisuke INOUE Mineo KANEKO Tsuyoshi IWAGAKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/04/01 Vol. E91-A No. 4 pp. 1044-1053 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 20th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: datapath synthesis, delay variation, register assignment, setup and hold constraints,
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Statistical Analysis Driven Synthesis of Application Specific Asynchronous Systems Koji OHASHI Mineo KANEKO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/03/01 Vol. E90-A No. 3 pp. 659-669 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: asynchronous system, scheduling, binding, statistical analysis,
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Characterization and Computation of Steiner Routing Based on Elmore's Delay Model Satoshi TAYU Mineo KANEKO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/12/01 Vol. E85-A No. 12 pp. 2764-2774 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Timing Analysis Keyword: Elmore's delay, Steiner tree, net, binary tree, Manhattan distance,
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Assignment-Driven Loop Pipeline Scheduling and Its Application to Data-Path Synthesis Toshiyuki YOROZUYA Koji OHASHI Mineo KANEKO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/04/01 Vol. E85-A No. 4 pp. 819-826 Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 14th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: data-path synthesis, resource assignment, loop pipeline scheduling, dependence graph, disjunctive arc,
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Reliable Data Routing for Spatial-Temporal TMR Multiprocessor Systems Mineo KANEKO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2001/12/01 Vol. E84-D No. 12 pp. 1790-1800 Type of Manuscript: PAPER Category: Fault Tolerance Keyword: systolic array, fault tolerance, on-line error correction, routing, network architecture, ,
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Checking Scheme for ABFT Systems Based on Modified PD Graph under an Error Generation/Propagation Model Choon-Sik PARK Mineo KANEKO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/06/25 Vol. E82-A No. 6 pp. 1002-1008 Type of Manuscript: Special Section PAPER (Special Section of Papers Selected from 1998 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC '98)) Category: Keyword: fault tolerance, processor-data graph, checking scheme, error model, fault detection, fault location,
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LMS-Based Algorithms with Multi-Band Decomposition of the Estimation Error Applied to System Identification Fernando Gil V. RESENDE,Jr Paulo S.R. DINIZ Keiichi TOKUDA Mineo KANEKO Akinori NISHIHARA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1997/08/25 Vol. E80-A No. 8 pp. 1376-1383 Type of Manuscript: Special Section PAPER (Special Section on Digital Signal Processing) Category: Keyword: adaptive signal processing, fixed and variable step-size LMS algorithms, filter banks, system identification,
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Multi-Band Decomposition of the Linear Prediction Error Applied to Adaptive AR Spectral Estimation Fernando Gil V. RESENDE Jr. Keiichi TOKUDA Mineo KANEKO Akinori NISHIHARA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1997/02/25 Vol. E80-A No. 2 pp. 365-376 Type of Manuscript: PAPER Category: Digital Signal Processing Keyword: digital signal processing, AR spectral estimation, filter banks, adaptive filtering, recursive least-squares algorithms,
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A Systematic Design of Fault Tolerant Systolic Arrays Based on Triple Modular Redundancy in Time-Processor Space Mineo KANEKO Hiroyuki MIYAUCHI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1996/12/25 Vol. E79-D No. 12 pp. 1676-1689 Type of Manuscript: PAPER Category: Fault Tolerant Computing Keyword: VLSI array processor, systolic array, fault tolerance, communication link, dependence graph,
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Adaptive AR Spectral Estimation Based on Wavelet Decomposition of the Linear Prediction Error Fernando Gil V. RESENDE Jr. Keiichi TOKUDA Mineo KANEKO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1996/05/25 Vol. E79-A No. 5 pp. 665-673 Type of Manuscript: PAPER Category: Digital Signal Processing Keyword: digital signal processing, spectral etimation, wavelet theory, adaptive fultering, recursive least-squares algorithms,
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Fault Tolerant Non-regular Digital Signal Processing Based on Computation Tree Block Decomposition Mineo KANEKO Hiroyuki MIYAUCHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1994/09/25 Vol. E77-A No. 9 pp. 1535-1545 Type of Manuscript: PAPER Category: Digital Signal Processing Keyword: fault tolerance, on-line error correction, signal flow graph, DSP algorithm,
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LIBRA: Automatic Performance-Driven Layout for Analog LSIs Tomohiko OHTSUKA Hiroaki KUNIEDA Mineo KANEKO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1992/03/25 Vol. E75-C No. 3 pp. 312-321 Type of Manuscript: Special Section PAPER (Special Issue on Analog LSI and Related Technology) Category: Keyword: performance-driven, process parameter, wire parasitics, performance deviation, simulated annealing, LIBRA,
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Two-Dimensional Quadrilateral Recursive Digital Filters with Parallel Structure--Synthesis and Parallel Processing-- Tsuyoshi ISSHIKI Hiroaki KUNIEDA Mineo KANEKO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1992/03/25 Vol. E75-A No. 3 pp. 352-361 Type of Manuscript: Special Section PAPER (Special Section on the 4th Karuizawa Workshop on Circuits and Systems) Category: Keyword: quadrilateral recursive filters, parallel processing,
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An Optimum Placement of Capacitors in the Layout of Switched Capacitor Networks Mineo KANEKO Kimihiko KAZUI Hiroaki KUNIEDA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1992/02/25 Vol. E75-A No. 2 pp. 215-223 Type of Manuscript: PAPER Category: Analog Circuits and Signal Processing Keyword: analog signal processing, VLSI design technology,
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MMAPC: An Effective Mixed-Mode Circuit Simulator Using Dynamic Circuit Partition Process Ben CHEN Mahoki ONODA Mineo KANEKO
Publication: IEICE TRANSACTIONS (1976-1990) Publication Date: 1988/04/25 Vol. E71-E No. 4 pp. 388-393 Type of Manuscript: PAPER Category: VLSI Design Technology Keyword:
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