Thomas Edison YU

Thermal-Aware Test Access Mechanism and Wrapper Design Optimization for System-on-Chips
Thomas Edison YU Tomokazu YONEDA Krishnendu CHAKRABARTY Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/10/01
Vol. E91-D  No. 10  pp. 2440-2448
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
SoC testing, test architecture design, test scheduling, thermal constraint, 
 Summary | Full Text:PDF
Effective Domain Partitioning for Multi-Clock Domain IP Core Wrapper Design under Power Constraints
Thomas Edison YU Tomokazu YONEDA Danella ZHAO Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/03/01
Vol. E91-D  No. 3  pp. 807-814
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
multi-clock domain, wrapper design, SoC, embedded core test, test scheduling, 
 Summary | Full Text:PDF