IEICE Trans - Test Scheduling for Multi-Clock Domain SoCs under Power Constraint

Test Scheduling for Multi-Clock Domain SoCs under Power Constraint

Tomokazu YONEDA  Kimihiko MASUDA  Hideo FUJIWARA

Publication
IEICE TRANSACTIONS on Information and Systems   Vol.E91-D   No.3   pp.747-755
Publication Date: 2008/03/01
Online ISSN: 1745-1361
DOI: 10.1093/ietisy/e91-d.3.747
Print ISSN: 0916-8532
Type of Manuscript: Special Section PAPER (Special Section on Test and Verification of VLSIs)
Category: High-Level Testing
Keyword:
multi-clock domain SoC,  test scheduling,  test access mechanism,  power consumption,

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Summary:
This paper presents a power-constrained test scheduling method for multi-clock domain SoCs that consist of cores operating at different clock frequencies during test. In the proposed method, we utilize virtual TAM to solve the frequency gaps between cores and the ATE. Moreover, we present a technique to reduce power consumption of cores during test while the test time of the cores remain the same or increase a little by using virtual TAM. Experimental results show the effectiveness of the proposed method.