For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
A DFT Selection Method for Reducing Test Application Time of System-on-Chips
Masahide MIYAZAKI Toshinori HOSOKAWA Hiroshi DATE Michiaki MURAOKA Hideo FUJIWARA
IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/03/01
Print ISSN: 0916-8532
Type of Manuscript: Special Section PAPER (Special Section on Test and Verification of VLSI)
Category: SoC Testing
test scheduling, test access mechanism, wrapper, design for test,
Full Text: PDF>>
This paper proposes an SoC test architecture generation framework. It contains a database, which stores the test cost information of several DFTs for every core, and a DFT selection part which performs DFT selection for minimizing the test application time using this database in the early phase of the design flow. Moreover, the DFT selection problem is formulated and the algorithm that solves this problem is proposed. Experimental results show that bottlenecks in test application time when using a single DFT method for all cores in an SoC is reduced by performing DFT selection from two types of DFTs. As a result, the whole test application time is drastically shortened.