IEICE Trans

Tomokazu YONEDA

An Effective and Sensitive Scan Segmentation Technique for Detecting Hardware Trojan Fakir Sharif HOSSAIN Tomokazu YONEDA Michiko INOUE
Publication: Publication Date: 2017/01/01 Vol. E100-D No. 1 pp. 130-139 Type of Manuscript: PAPER Category: Dependable Computing Keyword: hardware Trojan, scan segmentation, LoC patterns, power side-channel analysis, TDGP,
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Reliability-Enhanced ECC-Based Memory Architecture Using In-Field Self-Repair Gian MAYUGA Yuta YAMATO Tomokazu YONEDA Yasuo SATO Michiko INOUE
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2016/10/01 Vol. E99-D No. 10 pp. 2591-2599 Type of Manuscript: PAPER Category: Dependable Computing Keyword: memory repair, memory reliability, in-field test and repair, ECC, in-field repair strategy, remapping,
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Test Pattern Ordering and Selection for High Quality Test Set under Constraints Michiko INOUE Akira TAKETANI Tomokazu YONEDA Hideo FUJIWARA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2012/12/01 Vol. E95-D No. 12 pp. 3001-3009 Type of Manuscript: PAPER Category: Dependable Computing Keyword: small delay defects, SDQL, ATPG,
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Design and Optimization of Transparency-Based TAM for SoC Test Tomokazu YONEDA Akiko SHUTO Hideyuki ICHIHARA Tomoo INOUE Hideo FUJIWARA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2010/06/01 Vol. E93-D No. 6 pp. 1549-1559 Type of Manuscript: PAPER Category: Information Network Keyword: SoC test, design for testability, TAM design, transparency, ILP,
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Thermal-Aware Test Access Mechanism and Wrapper Design Optimization for System-on-Chips Thomas Edison YU Tomokazu YONEDA Krishnendu CHAKRABARTY Hideo FUJIWARA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2008/10/01 Vol. E91-D No. 10 pp. 2440-2448 Type of Manuscript: PAPER Category: Dependable Computing Keyword: SoC testing, test architecture design, test scheduling, thermal constraint,
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NoC-Compatible Wrapper Design and Optimization under Channel-Bandwidth and Test-Time Constraints Fawnizu Azmadi HUSSIN Tomokazu YONEDA Hideo FUJIWARA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2008/07/01 Vol. E91-D No. 7 pp. 2008-2017 Type of Manuscript: PAPER Category: Dependable Computing Keyword: SoC testing, NoC testing, test wrapper design, NoC-compatible wrapper,
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On NoC Bandwidth Sharing for the Optimization of Area Cost and Test Application Time Fawnizu Azmadi HUSSIN Tomokazu YONEDA Hideo FUJIWARA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2008/07/01 Vol. E91-D No. 7 pp. 1999-2007 Type of Manuscript: PAPER Category: Dependable Computing Keyword: SoC test scheduling, test wrapper, test access mechanism, NoC-reuse, bandwidth sharing,
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Effective Domain Partitioning for Multi-Clock Domain IP Core Wrapper Design under Power Constraints Thomas Edison YU Tomokazu YONEDA Danella ZHAO Hideo FUJIWARA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2008/03/01 Vol. E91-D No. 3 pp. 807-814 Type of Manuscript: PAPER Category: Dependable Computing Keyword: multi-clock domain, wrapper design, SoC, embedded core test, test scheduling,
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Scheduling Power-Constrained Tests through the SoC Functional Bus Fawnizu Azmadi HUSSIN Tomokazu YONEDA Alex ORAILOLU Hideo FUJIWARA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2008/03/01 Vol. E91-D No. 3 pp. 736-746 Type of Manuscript: Special Section PAPER (Special Section on Test and Verification of VLSIs) Category: High-Level Testing Keyword: functional bus, functional TAM, power-constrained, packet-based scheduling, system-on-chip testing,
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Test Scheduling for Multi-Clock Domain SoCs under Power Constraint Tomokazu YONEDA Kimihiko MASUDA Hideo FUJIWARA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2008/03/01 Vol. E91-D No. 3 pp. 747-755 Type of Manuscript: Special Section PAPER (Special Section on Test and Verification of VLSIs) Category: High-Level Testing Keyword: multi-clock domain SoC, test scheduling, test access mechanism, power consumption,
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A Memory Grouping Method for Reducing Memory BIST Logic of System-on-Chips Masahide MIYAZAKI Tomokazu YONEDA Hideo FUJIWARA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2006/04/01 Vol. E89-D No. 4 pp. 1490-1497 Type of Manuscript: PAPER Category: Dependable Computing Keyword: SoC, test scheduling, wrapper, design for test, memory BIST,
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