Keyword : test access mechanism

On NoC Bandwidth Sharing for the Optimization of Area Cost and Test Application Time
Fawnizu Azmadi HUSSIN Tomokazu YONEDA Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/07/01
Vol. E91-D  No. 7 ; pp. 1999-2007
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
SoC test scheduling, test wrapper, test access mechanism, NoC-reuse, bandwidth sharing, 
 Summary | Full Text:PDF
Test Scheduling for Multi-Clock Domain SoCs under Power Constraint
Tomokazu YONEDA Kimihiko MASUDA Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/03/01
Vol. E91-D  No. 3 ; pp. 747-755
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSIs)
Category: High-Level Testing
Keyword: 
multi-clock domain SoC, test scheduling, test access mechanism, power consumption, 
 Summary | Full Text:PDF
A DFT Selection Method for Reducing Test Application Time of System-on-Chips
Masahide MIYAZAKI Toshinori HOSOKAWA Hiroshi DATE Michiaki MURAOKA Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/03/01
Vol. E87-D  No. 3 ; pp. 609-619
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSI)
Category: SoC Testing
Keyword: 
test scheduling, test access mechanism, wrapper, design for test, 
 Summary | Full Text:PDF