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IEICE Trans

Hiroshi DATE

A DFT Selection Method for Reducing Test Application Time of System-on-Chips
Masahide MIYAZAKI Toshinori HOSOKAWA Hiroshi DATE Michiaki MURAOKA Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/03/01
Vol. E87-D  No. 3  pp. 609-619
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSI)
Category: SoC Testing
Keyword: 
test scheduling, test access mechanism, wrapper, design for test, 
 Summary | Full Text:PDF
A Test Plan Grouping Method to Shorten Test Length for RTL Data Paths under a Test Controller Area Constraint
Toshinori HOSOKAWA Hiroshi DATE Masahide MIYAZAKI Michiaki MURAOKA Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/12/01
Vol. E86-D  No. 12  pp. 2674-2683
Type of Manuscript:  Special Section PAPER (Special Issue on Dependable Computing)
Category: Test
Keyword: 
test plan grouping, test controllers, partly compacted test plan tables, RTL data paths, hierarchical test generation, 
 Summary | Full Text:PDF
Two Test Generation Methods Using a Compacted Test Table and a Compacted Test Plan Table for RTL Data Path Circuits
Toshinori HOSOKAWA Hiroshi DATE Michiaki MURAOKA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/10/01
Vol. E85-D  No. 10  pp. 1474-1482
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Verification of VLSI)
Category: Test Generation and Modification
Keyword: 
test generation, test plans, compacted test plan tables, test plan compatibility graph, RTL data path, 
 Summary | Full Text:PDF
Hierarchical Intellectual Property Protection Using Partially-Mergeable Cores
Vikram IYENGAR Hiroshi DATE Makoto SUGIHARA Krishnendu CHAKRABARTY 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11  pp. 2632-2638
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: IP Protection
Keyword: 
core partitioning, embedded core testing, intellectual property, partially-mergeable cores, test access mechanism (TAM), 
 Summary | Full Text:PDF
A Test Methodology for Core-Based System LSIs
Makoto SUGIHARA Hiroshi DATE Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A  No. 12  pp. 2640-2645
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Test
Keyword: 
testing time, core-based system LSI, BIST, external testing, 
 Summary | Full Text:PDF