Hierarchical Intellectual Property Protection Using Partially-Mergeable Cores

Vikram IYENGAR  Hiroshi DATE  Makoto SUGIHARA  Krishnendu CHAKRABARTY  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E84-A   No.11   pp.2632-2638
Publication Date: 2001/11/01
Online ISSN: 
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: IP Protection
core partitioning,  embedded core testing,  intellectual property,  partially-mergeable cores,  test access mechanism (TAM),  

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We present a new technique for hierarchical intellectual property (IP) protection using partially-mergeable cores. The proposed core partitioning technique guarantees 100% protection of critical-IP, while simplifying test generation for the logic that is merged with the system. Since critical-IP is tested using BIST, the controllability and observability of internal lines in the core are enhanced, and test application time is reduced. Case studies using the ISIT-DLX and Picojava processor cores demonstrate the applicability of our technique.