Krishnendu CHAKRABARTY

Thermal-Aware Test Access Mechanism and Wrapper Design Optimization for System-on-Chips
Thomas Edison YU Tomokazu YONEDA Krishnendu CHAKRABARTY Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/10/01
Vol. E91-D  No. 10  pp. 2440-2448
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
SoC testing, test architecture design, test scheduling, thermal constraint, 
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Hierarchical Intellectual Property Protection Using Partially-Mergeable Cores
Vikram IYENGAR Hiroshi DATE Makoto SUGIHARA Krishnendu CHAKRABARTY 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11  pp. 2632-2638
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: IP Protection
Keyword: 
core partitioning, embedded core testing, intellectual property, partially-mergeable cores, test access mechanism (TAM), 
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