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| Keyword : latency
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Switch-Based Quorum Coordination for Low Tail Latency in Replicated Storage
Gyuyeong KIM | Publication: IEICE TRANSACTIONS on Information and Systems
Publication Date: 2023/11/01
Vol. E106-D
No. 11 ;
pp. 1922-1925
Type of Manuscript:
LETTER
Category: Information Network
Keyword:
in-network computing, programmable switches, latency, | | | Summary | Full Text:PDF | |
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Field Evaluation of 5G Low Latency and High Reliability Vehicle-to-Vehicle Direct Communication for Application to Truck Platooning
Manabu MIKAMI Koichi SERIZAWA Kohei MOTO Hitoshi YOSHINO | Publication: IEICE TRANSACTIONS on Communications
Publication Date: 2021/09/01
Vol. E104-B
No. 9 ;
pp. 1026-1034
Type of Manuscript:
Special Section PAPER (Special Section on Technology Trials and Proof-of-Concept Activities for 5G Evolution and Beyond)
Category:
Keyword:
5G V2V direct, latency, reliability, truck platooning, | | | Summary | Full Text:PDF | |
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MAC 2: A Multi-Hop Adaptive MAC Protocol with Packet Concatenation for Wireless Sensor Networks
Kien NGUYEN Ulrich MEIS Yusheng JI | Publication: IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/02/01
Vol. E95-D
No. 2 ;
pp. 480-489
Type of Manuscript:
Special Section PAPER (Special Section on Architectures, Protocols, and Applications for the Future Internet)
Category:
Keyword:
multi-hop MAC, energy efficient, latency, throughput, | | | Summary | Full Text:PDF | |
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Evaluation of Cognitive Function Using Event-Related Potential (P300 and CNV): Comparison among Young, Middle-Aged, and Elderly People
Atsuo MURATA Takashi SORA | Publication: IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/04/01
Vol. E87-D
No. 4 ;
pp. 992-996
Type of Manuscript:
PAPER
Category: Rehabilitation Engineering and Assistive Technology
Keyword:
P300, CNV, aging, latency, amplitude, | | | Summary | Full Text:PDF | |
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High Speed DRAMs with Innovative Architectures
Shigeo OHSHIMA Tohru FURUYAMA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1994/08/25
Vol. E77-C
No. 8 ;
pp. 1303-1315
Type of Manuscript:
INVITED PAPER (Special Section on High Speed and High Density Multi Functional LSI Memories)
Category: DRAM
Keyword:
DRAM, memory bottleneck, data bandwidth, latency, synchronous DRAM, pipeline architecture, data prefetching, cache DRAM, fast copyback, Rambus interface, Rambus DRAM, protocol packet, PLL, | | | Summary | Full Text:PDF | |
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