DDR3 SDRAM with a Complete Predictor

Vladimir V. STANKOVIC  Nebojsa Z. MILENKOVIC  

IEICE TRANSACTIONS on Information and Systems   Vol.E93-D   No.9   pp.2635-2638
Publication Date: 2010/09/01
Online ISSN: 1745-1361
DOI: 10.1587/transinf.E93.D.2635
Print ISSN: 0916-8532
Type of Manuscript: LETTER
Category: Computer System
DDR3 SDRAM,  latency,  predictor,  

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In the arsenal of resources for improving computer memory system performance, predictors have gained an increasing role in the past few years. They enable hiding the latencies when accessing cache or main memory. In our previous work we proposed a DDR SDRAM controller with predictors that not only close the opened DRAM row but also predict the next row to be opened. In this paper we explore the possibilities of trying the same techniques on the latest type of DRAM memory, DDR3 SDRAM, with further improvements of the predictors.