Keyword : circuit simulation network tearing

Hierarchical Decomposition and Latency for Circuit Simulation by Direct Method
Masakatsu NISHIGAKI Nobuyuki TANAKA Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/03/25
Vol. E75-A  No. 3 ; pp. 347-351
Type of Manuscript:  Special Section LETTER (Special Section on the 4th Karuizawa Workshop on Circuits and Systems)
circuit simulation network tearinghierarchical decompositionlatency
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