Masakatsu NISHIGAKI


Relaxation-Based Algorithms for Bipolar Circuit Analysis
Masaki ISHIDA Koichi HAYASHI Masakatsu NISHIGAKI Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/06/25
Vol. E77-A  No. 6  pp. 1023-1027
Type of Manuscript:  Special Section PAPER (Special Section of Papers Selected from 1993 Joint Technical Conference on Circuits/Systems, Computers and Communications (JTC-CSCC'93))
Category: Modeling and Simulation
Keyword: 
circuit simulationdynamic partitioningITAwaveform relaxationbipolar circit
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Mixed Mode Circuit Simulation Using Dynamic Network Separation and Selective Trace
Masakatsu NISHIGAKI Nobuyuki TANAKA Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/03/25
Vol. E77-A  No. 3  pp. 454-460
Type of Manuscript:  Special Section PAPER (Special Section on the 6th Karuizawa Workshop on Circuits and Systems)
Category: Modeling and Simulation
Keyword: 
mixed mode circuit simulationdynamic partitioningnetwork separationlatencyselective trace
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Mixed Mode Circuit Simulation Using Dynamic Partitioning
Masakatsu NISHIGAKI Nobuyuki TANAKA Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/03/25
Vol. E76-A  No. 3  pp. 292-298
Type of Manuscript:  Special Section PAPER (Special Section on the 5th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
circuit simulationmixed mode simulationdynamic partitioninghierarchical decompositionlatency
 Summary | Full Text:PDF

Bipolar Transistor Circuit Analysis by Waveform Relaxation Method with Consideration of the Operation Point
Koichi HAYASHI Mitsuru KOMATSU Masakatsu NISHIGAKI Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/07/25
Vol. E75-A  No. 7  pp. 914-916
Type of Manuscript:  Special Section LETTER (Special Section on the 1992 IEICE Spring Conference)
Category: 
Keyword: 
circuit simulationwaveform relaxationdynamic partitioningbipolar transistor circuit
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Hierarchical Decomposition and Latency for Circuit Simulation by Direct Method
Masakatsu NISHIGAKI Nobuyuki TANAKA Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/03/25
Vol. E75-A  No. 3  pp. 347-351
Type of Manuscript:  Special Section LETTER (Special Section on the 4th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
circuit simulation network tearinghierarchical decompositionlatency
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Hierarchical Decomposition for Circuit Simulation by Direct Method
Masakatsu NISHIGAKI Nobuyuki TANAKA Hideki ASAI 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1990/12/25
Vol. E73-E  No. 12  pp. 1948-1956
Type of Manuscript:  Special Section PAPER (Special Issue on the 3rd Karuizawa Workshop on Circuits and Systems)
Category: Nonlinear Circuits and Simulation
Keyword: 
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