Power and Skew Aware Point Diffusion Clock Network

Gunok JUNG  Chunghee KIM  Kyoungkuk CHAE  Giho PARK  Sung Bae PARK  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E91-C   No.11   pp.1832-1834
Publication Date: 2008/11/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e91-c.11.1832
Print ISSN: 0916-8516
Type of Manuscript: LETTER
Category: Integrated Electronics
Keyword: 
clock network,  skew,  latency,  low power,  

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Summary: 
This letter presents point diffusion clock network (PDCN) with local clock tree synthesis (CTS) scheme. The clock network is implemented with ten times wider metal line space than typical mesh networks for low power and utilized to nine times smaller area CTS execution for minimized clock skew amount. The measurement results show that skew amount of PDCN with local CTS is reduced to 36% and latency is shrunk to 45% of the amount in a 4.81 mm2 CortexA-8 core with 65 nm Samsung process.