|
| Keyword : LSI
| |
|
Sub-10 nm Multi-Nano-Pillar Type Vertical MOSFET
Tetsuo ENDOH Koji SAKUI Yukio YASUDA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2010/05/01
Vol. E93-C
No. 5 ;
pp. 557-562
Type of Manuscript:
Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: Emerging Devices
Keyword:
vertical MOSFET, 3D structured device, MOSFET, LSI, | | | Summary | Full Text:PDF | |
| |
| |
| |
|
The Front-End LSI with a 5-Tap PRML for 2 Reading and Writing of BD-R/RW/ROM
GoangSeog CHOI JumHan BAE HyunSoo PARK | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2007/04/01
Vol. E90-C
No. 4 ;
pp. 727-730
Type of Manuscript:
Special Section LETTER (Special Section on Low-Power, High-Speed LSIs and Related Technologies)
Category: Digital
Keyword:
BD, LSI, PRML, OPC, Viterbi detector, | | | Summary | Full Text:PDF | |
|
Design of a Neural Network Chip for the Burst ID Model with Ability of Burst Firing
Shinya SUENAGA Yoshihiro HAYAKAWA Koji NAKAJIMA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/04/01
Vol. E90-A
No. 4 ;
pp. 715-723
Type of Manuscript:
Special Section PAPER (Special Section on Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa)
Category:
Keyword:
burst firing, neural network, optimization problem, LSI, | | | Summary | Full Text:PDF | |
| |
| |
| |
| |
|
A New Description of MOS Circuits at Switch-Level with Applications
Massoud PEDRAM Xunwei WU | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/10/25
Vol. E80-A
No. 10 ;
pp. 1892-1901
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category:
Keyword:
MOS, LSI, pass-transistor logic, switching theory, low power design, | | | Summary | Full Text:PDF | |
| |
| |
|
A Learning Algorithm for a Neural Network LSI with Restricted Integer Weights
Tomohisa KIMURA Takeshi SHIMA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1997/07/25
Vol. E80-C
No. 7 ;
pp. 983-989
Type of Manuscript:
Special Section PAPER (Special Issue on New Concept Device and Novel Architecture LSIs)
Category: Neural Networks and Chips
Keyword:
neural networks, learning, analog, LSI, accuracy, | | | Summary | Full Text:PDF | |
| |
|
Low Power Design Technology for Digital LSIs
Tadayoshi ENOMOTO | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1996/12/25
Vol. E79-C
No. 12 ;
pp. 1639-1649
Type of Manuscript:
INVITED PAPER (Special Issue on Low-Power LSI Technologies)
Category:
Keyword:
power dissipation, active power dissipation, stand-by power dissipation, low power circuit technology, LSI, CMOS LSIs, GaAs LSIs, mlulti-media LSIs, video codec LSIs, signal handling capability, throughput, clock frequency, video signal processor, VSP, DSP. H.261, MPEG2, | | | Summary | Full Text:PDF | |
|
VLSI-Oriented Input and Output Buffered Switch Architecture for High-Speed ATM Backbone Nodes
Yukio KAMATANI Yoshihiro OHBA Yoshimitsu SHIMOJO Koutarou ISE Masahiko MOTOYAMA Toshitada SAITO | Publication: IEICE TRANSACTIONS on Communications
Publication Date: 1996/05/25
Vol. E79-B
No. 5 ;
pp. 647-657
Type of Manuscript:
Special Section PAPER (Special Issue on High Speed Local Area Network)
Category:
Keyword:
ATM, switch, node, high-speed, backbone, flow control, input buffer, output buffer, shared buffer, multicast, QoS, LSI, | | | Summary | Full Text:PDF | |
|
An Analytical Modeling of Three Primary Wiring Capacitance Components for Multi-Layer Interconnect Structure
Susumu KUROSAWA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/12/25
Vol. E78-A
No. 12 ;
pp. 1793-1798
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category:
Keyword:
capacitance, modeling, interconnect, LSI, LPE, | | | Summary | Full Text:PDF | |
| |
| |
| |
|
Development of Improved Low Power MUSE (HDTV) Decoder Chip Set 2.5th Generation MUSE Chip Set
Kiyoshi KOHIYAMA Kota OTSUBO Hidenaga TAKAHASHI Kiyotaka OGAWA Yukio OTOBE | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1994/12/25
Vol. E77-C
No. 12 ;
pp. 1859-1864
Type of Manuscript:
Special Section PAPER (Special Issue on Multimedia, Analog and Processing LSIs)
Category: Multimedia System LSIs
Keyword:
HDTV, MUSE, LSI, power, | | | Summary | Full Text:PDF | |
| |
|
Research Topics and Results on Analog Circuit Design for LSI
Nobuo FUJII | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/07/25
Vol. E76-A
No. 7 ;
pp. 1061-1069
Type of Manuscript:
Special Section PAPER (Special Section on Surveys of Researches in CAS Fields in the Last Two Decades, I)
Category:
Keyword:
analog circuits, LSI, | | | Summary | Full Text:PDF | |
| |
| |
| |
| |
| |
|
An MOS Operational Transconductance Amplifier and an MOS Four-Quadrant Analog Multiplier Using the Quadritail Cell
Katsuji KIMURA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/12/25
Vol. E75-A
No. 12 ;
pp. 1774-1776
Type of Manuscript:
Special Section LETTER (Special Section on the 1992 IEICE Fall Conference)
Category:
Keyword:
OTA, multiplier, transconductance, quadritail cell, MOS, LSI, | | | Summary | Full Text:PDF | |
|
Isolation Characteristics in GaAs ICs on Semi-Insulating Substrate
Kazuyuki INOKUCHI Yuko SEKINO-ITOH Yoshiaki SANO | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1992/10/25
Vol. E75-C
No. 10 ;
pp. 1154-1164
Type of Manuscript:
Special Section PAPER (Special Issue on Compound Semiconductor Integrated Circuits)
Category:
Keyword:
isolation, leak, sidegate, M-i-n, LSI, | | | Summary | Full Text:PDF | |
|
|