Low Power Design Technology for Digital LSIs

Tadayoshi ENOMOTO  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E79-C   No.12   pp.1639-1649
Publication Date: 1996/12/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: INVITED PAPER (Special Issue on Low-Power LSI Technologies)
Category: 
Keyword: 
power dissipation,  active power dissipation,  stand-by power dissipation,  low power circuit technology,  LSI,  CMOS LSIs,  GaAs LSIs,  mlulti-media LSIs,  video codec LSIs,  signal handling capability,  throughput,  clock frequency,  video signal processor,  VSP,  DSP. H.261,  MPEG2,  

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Summary: 
Discussed here is reduction of power dissipation for multi-media LSIs. First, both active power dissipation Pat and stand-by power dissipation Pst for both CMOS LSIs and GaAs LSIs are summarized. Then, general technologies for reducing Pat are discussed. Also reviewed are a wide variety of approaches (i.e., parallel and pipeline schemes, Chen's fast DCT algorithms, hierarchical search scheme for motion vectors, etc.) for reduction of Pat. The last part of the paper focuses on reduction of Pst. Reducing both Pat and Pst requires that both throughput and active chip areas be either maintained or improved.