A Shared Multibuffer Architecture for High-Speed ATM Switch LSIs

Harufusa KONDOH  Hiromi NOTANI  Hideaki YAMANAKA  Keiichi HIGASHITANI  Hirotaka SAITO  Isamu HAYASHI  Yoshio MATSUDA  Kazuyoshi OSHIMA  Masao NAKAYA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E76-C   No.7   pp.1094-1101
Publication Date: 1993/07/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on New Architecture LSIs)
Category: Improved Binary Digital Architectures
Keyword: 
B-ISDN,  ATM,  switch,  LSI,  BiCMOS,  

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Summary: 
A new shared multibuffer architecture for high-speed ATM (Asynchronous Transfer Mode) switch LSIs is described. Multiple buffer memories are located between two crosspoint switches. By controlling the input-side crosspoint switch so as to equalize the utilization rate of each buffer memory, these multiple buffer memories can be recognized as a single large shared buffer memory. High utilization efficiency of buffer memory can thus be achieved, and the cell loss ratio is minimized. By accessing the buffer memories in parallel via crosspoint switches, the time required to access the buffer memories is greatly reduced. This feature enables high-speed operation of the switch. The shared multibuffer architecture was implemented in a switch LSI using 0.8-µm BiCMOS process technology. Experimental results revealed that this chip can operate at more than 125 MHz. Bit-sliced eight switch LSIs operating at 78 MHz construct a 622-Mb/s 88 ATM switching system with a buffer size of 1,024 ATM cells. Power consumption of the switch LSI was 3 W.