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| Keyword : ASIC
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Compact Architecture for ASIC and FPGA Implementation of the KASUMI Block Cipher
Dai YAMAMOTO Kouichi ITOH Jun YAJIMA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A
No. 12 ;
pp. 2628-2638
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword:
block cipher, KASUMI, hardware, ASIC, FPGA, compact implementation, | | | Summary | Full Text:PDF | |
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Compact Architecture for ASIC Implementation of the MISTY1 Block Cipher
Dai YAMAMOTO Jun YAJIMA Kouichi ITOH | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/01/01
Vol. E93-A
No. 1 ;
pp. 3-12
Type of Manuscript:
Special Section PAPER (Special Section on Cryptography and Information Security)
Category: Symmetric Cryptography
Keyword:
block cipher, MISTY1, hardware, ASIC, compact implementation, | | | Summary | Full Text:PDF | |
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Hardware Design Verification Using Signal Transitions and Transactions
Nobuyuki OHBA Kohji TAKANO | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/04/01
Vol. E89-A
No. 4 ;
pp. 1012-1017
Type of Manuscript:
Special Section PAPER (Special Section on Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
Category:
Keyword:
hardware prototyping, hardware debugging, logic analyzer, ASIC, SoC, | | | Summary | Full Text:PDF | |
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A New Implementation Technique to Decode the Convolutional Code in Trellis-Coded Modulation
Anh DINH Xiao HU | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/03/01
Vol. E87-A
No. 3 ;
pp. 619-627
Type of Manuscript:
Special Section PAPER (Special Section on Applications and Implementations of Digital Signal Processing)
Category: Communication Theory and Systems
Keyword:
TCM, look-up-table, Viterbi decoding, IP core, ASIC, VLSI architecture, | | | Summary | Full Text:PDF | |
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Low-Power Architectures for Programmable Multimedia Processors
Takao NISHITANI | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/02/25
Vol. E82-A
No. 2 ;
pp. 184-196
Type of Manuscript:
INVITED PAPER (Special Section on VLSI for Digital Signal Processing)
Category:
Keyword:
multimedia processors, SOC, ASIC, MPU, DSP, | | | Summary | Full Text:PDF | |
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An On-Line Scheduler for ASIC Manufacturing Line Management
Tadao TAKEDA Satoshi TAZAWA Kou WADA Eisuke ARAI | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1995/03/25
Vol. E78-C
No. 3 ;
pp. 241-247
Type of Manuscript:
Special Section PAPER (Special Issue on Sub-1/4 Micron Device and Process Technologies)
Category:
Keyword:
scheduler, ASIC, TAT, algorithm, | | | Summary | Full Text:PDF | |
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