Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2015/07/01 Vol. E98-CNo. 7 ;
pp. 594-596 Type of Manuscript: BRIEF PAPER Category: Keyword: error control code, parallel architecture, LFSR, BCH,
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2013/05/01 Vol. E96-BNo. 5 ;
pp. 1211-1214 Type of Manuscript: LETTER Category: Fundamental Theories for Communications Keyword: turbo decoder, parallel architecture, LTE, 4G,
Parallel Architecture for 2-D Discrete Wavelet Transform with Low Energy Consumption Nozomi ISHIHARAKoki ABE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/08/01 Vol. E91-ANo. 8 ;
pp. 2068-2075 Type of Manuscript: PAPER Category: Digital Signal Processing Keyword: DWT, signal processing, parallel architecture, efficient memory access, burst access, ASIC,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/06/25 Vol. E82-ANo. 6 ;
pp. 939-944 Type of Manuscript: Special Section PAPER (Special Section of Papers Selected from 1998 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC '98)) Category: Keyword: SIMD, vector processing, parallel architecture, video signal processing, digital signal processing,
A Parallel Hardware Architecture for Accelerating α-β Game Tree Search Yi-Fan KETai-Ming PARNG
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1996/09/25 Vol. E79-DNo. 9 ;
pp. 1232-1240 Type of Manuscript: PAPER Category: Computer Hardware and Design Keyword: parallel search, parallel architecture, computer chess, α-β algorithm,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1996/09/25 Vol. E79-ANo. 9 ;
pp. 1313-1323 Type of Manuscript: Special Section PAPER (Special Section on Information Theory and Its Applications) Category: Coding Theory Keyword: error correction, cyclic code, parallel architecture, circuit design, encoder, decoder,
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1995/05/25 Vol. E78-DNo. 5 ;
pp. 586-595 Type of Manuscript: PAPER Category: Image Processing, Computer Graphics and Pattern Recognition Keyword: parallel architecture, motion estimation algorithm, video coding,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1993/06/25 Vol. E76-ANo. 6 ;
pp. 947-956 Type of Manuscript: Special Section PAPER (Special Section on Papers Selected from 1992 Joint Technical Conference on Circuits/Systems,Computers and Communications (JTC-CSCC'92)) Category: Methods and Circuits for Signal Processing Keyword: parallel processing, load balancing, video CODEC, parallel architecture, reconfigurable architecture,
