Parallel Architecture for 2-D Discrete Wavelet Transform with Low Energy Consumption

Nozomi ISHIHARA  Koki ABE  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E91-A   No.8   pp.2068-2075
Publication Date: 2008/08/01
Online ISSN: 1745-1337
DOI: 10.1093/ietfec/e91-a.8.2068
Print ISSN: 0916-8508
Type of Manuscript: PAPER
Category: Digital Signal Processing
DWT,  signal processing,  parallel architecture,  efficient memory access,  burst access,  ASIC,  

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A novel two-dimensional discrete wavelet transform (2-DDWT) parallel architecture for higher throughput and lower energy consumption is proposed. The proposed architecture fully exploits full-page burst accesses of DRAM and minimizes the number of DRAM activate and precharge operations. Simulation results revealed that the architecture reduces the number of clock cycles for DRAM memory accesses as well as the DRAM power consumption with moderate cost of internal memory. Evaluation of the VLSI implementation of the architecture showed that the throughput of wavelet filtering was increased by parallelizing row filtering with a minimum area cost, thereby enabling DRAM full-page burst accesses to be exploited.