Keyword : row sliceable


High-Performance Memory Macrocells with Row and Column Sliceable Architecture
Nobutaro SHIBATA Yoshinori GOTOH Shigeru DATE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/11/25
Vol. E76-C  No. 11 ; pp. 1641-1648
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Memories)
Category: Application Specific Memory
Keyword: 
ASICCMOSmacrocellmemoryconfigurablerow sliceabledecodershort design Turn-Around-Time (TAT)
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