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IEICE Trans

Naoya ONIZAWA

High-Accuracy and Area-Efficient Stochastic FIR Digital Filters Based on Hybrid Computation
Shunsuke KOSHITA Naoya ONIZAWA Masahide ABE Takahiro HANYU Masayuki KAWAMATA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2017/08/01
Vol. E100-D  No. 8  pp. 1592-1602
Type of Manuscript:  Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)
Category: VLSI Architecture
Keyword: 
FIR digital filter, stochastic computation, computational accuracy, digital circuit implementation, 
 Summary | Full Text:PDF
Asynchronous Stochastic Decoding of LDPC Codes: Algorithm and Simulation Model
Naoya ONIZAWA Warren J. GROSS Takahiro HANYU Vincent C. GAUDET 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/09/01
Vol. E97-D  No. 9  pp. 2286-2295
Type of Manuscript:  Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)
Category: VLSI Architecture
Keyword: 
forward error correction (FEC), stochastic computation, asynchronous circuits, 
 Summary | Full Text:PDF
High-Throughput Partially Parallel Inter-Chip Link Architecture for Asynchronous Multi-Chip NoCs
Naoya ONIZAWA Akira MOCHIZUKI Hirokatsu SHIRAHAMA Masashi IMAI Tomohiro YONEDA Takahiro HANYU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/06/01
Vol. E97-D  No. 6  pp. 1546-1556
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
Asynchronous circuits, Network-on-Chip (NoC), burst-mode data transmission, level-encoded dual-rail (LEDR) encoding, error detection, data retransmission, 
 Summary | Full Text:PDF
Open-Fault Resilient Multiple-Valued Codes for Reliable Asynchronous Global Communication Links
Naoya ONIZAWA Atsushi MATSUMOTO Takahiro HANYU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/09/01
Vol. E96-D  No. 9  pp. 1952-1961
Type of Manuscript:  Special Section PAPER (Special Section on Dependable Computing)
Category: 
Keyword: 
fault tolerance, m-of-n codes, error detection codes, bidirectional communication, 
 Summary | Full Text:PDF
Long-Range Asynchronous On-Chip Link Based on Multiple-Valued Single-Track Signaling
Naoya ONIZAWA Atsushi MATSUMOTO Takahiro HANYU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/06/01
Vol. E95-A  No. 6  pp. 1018-1029
Type of Manuscript:  PAPER
Category: Circuit Theory
Keyword: 
delay-insensitive, asynchronous circuits, multiple-valued current-mode (MVCM) circuits, Network-on-Chip (NoC), communication link, 
 Summary | Full Text:PDF
Highly Reliable Multiple-Valued One-Phase Signalling for an Asynchronous On-Chip Communication Link
Naoya ONIZAWA Takahiro HANYU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/08/01
Vol. E93-D  No. 8  pp. 2089-2099
Type of Manuscript:  Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)
Category: Multiple-Valued VLSI Technology
Keyword: 
delay-insensitive, asynchronous circuits, multiple-valued current-mode (MVCM) circuits, Network-on-Chip (NoC), communication link, 
 Summary | Full Text:PDF
High-Throughput Bit-Serial LDPC Decoder LSI Based on Multiple-Valued Asynchronous Interleaving
Naoya ONIZAWA Takahiro HANYU Vincent C. GAUDET 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/06/01
Vol. E92-C  No. 6  pp. 867-874
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
error control coding, LDPC codes, sum-product algorithm, asynchronous data transfer, multiple-valued current-mode circuit, 
 Summary | Full Text:PDF
Power-Aware Asynchronous Peer-to-Peer Duplex Communication System Based on Multiple-Valued One-Phase Signaling
Kazuyasu MIZUSAWA Naoya ONIZAWA Takahiro HANYU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/04/01
Vol. E91-C  No. 4  pp. 581-588
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories)
Category: 
Keyword: 
delay-insensitive, dual-rail encoding, multiple-valued current-mode (MVCM) circuit, peer-to-peer communication, 
 Summary | Full Text:PDF
Design and Evaluation of a NULL-Convention Circuit Based on Dual-Rail Current-Mode Differential Logic
Naoya ONIZAWA Takahiro HANYU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/11/01
Vol. E89-C  No. 11  pp. 1575-1580
Type of Manuscript:  Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies)
Category: 
Keyword: 
asynchronous logic design, self-timed circuit, differential-pair circuit, delay insensitive, 
 Summary | Full Text:PDF
Differential Operation Oriented Multiple-Valued Encoding and Circuit Realization for Asynchronous Data Transfer
Tomohiro TAKAHASHI Naoya ONIZAWA Takahiro HANYU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/11/01
Vol. E87-C  No. 11  pp. 1928-1934
Type of Manuscript:  Special Section PAPER (Special Section on New System Paradigms for Integrated Electronics)
Category: 
Keyword: 
differential operation, delay-insensitive, dual-rail encoding, point-to-point communication, 
 Summary | Full Text:PDF