IEICE Trans

Takahiro HANYU

High-Accuracy and Area-Efficient Stochastic FIR Digital Filters Based on Hybrid Computation Shunsuke KOSHITA Naoya ONIZAWA Masahide ABE Takahiro HANYU Masayuki KAWAMATA
Publication: Publication Date: 2017/08/01 Vol. E100-D No. 8 pp. 1592-1602 Type of Manuscript: Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing) Category: VLSI Architecture Keyword: FIR digital filter, stochastic computation, computational accuracy, digital circuit implementation,
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FOREWORD Takahiro HANYU
Publication: Publication Date: 2017/08/01 Vol. E100-D No. 8 pp. 1555-1555 Type of Manuscript: FOREWORD Category: Keyword:
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Energy-Efficient and Highly-Reliable Nonvolatile FPGA Using Self-Terminated Power-Gating Scheme Daisuke SUZUKI Takahiro HANYU
Publication: Publication Date: 2017/08/01 Vol. E100-D No. 8 pp. 1618-1624 Type of Manuscript: Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing) Category: VLSI Architecture Keyword: field-programmable gate array (FPGA), power gating, magnetic tunnel junction (MTJ) device, and low power digital,
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Design of an Energy-Efficient Ternary Current-Mode Intra-Chip Communication Link for an Asynchronous Network-on-Chip Akira MOCHIZUKI Hirokatsu SHIRAHAMA Yuma WATANABE Takahiro HANYU
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2014/09/01 Vol. E97-D No. 9 pp. 2304-2311 Type of Manuscript: Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing) Category: Communication for VLSI Keyword: asynchronous communication link, network-on-chip, multiple-valued logic, current-mode,
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Asynchronous Stochastic Decoding of LDPC Codes: Algorithm and Simulation Model Naoya ONIZAWA Warren J. GROSS Takahiro HANYU Vincent C. GAUDET
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2014/09/01 Vol. E97-D No. 9 pp. 2286-2295 Type of Manuscript: Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing) Category: VLSI Architecture Keyword: forward error correction (FEC), stochastic computation, asynchronous circuits,
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High-Throughput Partially Parallel Inter-Chip Link Architecture for Asynchronous Multi-Chip NoCs Naoya ONIZAWA Akira MOCHIZUKI Hirokatsu SHIRAHAMA Masashi IMAI Tomohiro YONEDA Takahiro HANYU
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2014/06/01 Vol. E97-D No. 6 pp. 1546-1556 Type of Manuscript: PAPER Category: Dependable Computing Keyword: Asynchronous circuits, Network-on-Chip (NoC), burst-mode data transmission, level-encoded dual-rail (LEDR) encoding, error detection, data retransmission,
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Open-Fault Resilient Multiple-Valued Codes for Reliable Asynchronous Global Communication Links Naoya ONIZAWA Atsushi MATSUMOTO Takahiro HANYU
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2013/09/01 Vol. E96-D No. 9 pp. 1952-1961 Type of Manuscript: Special Section PAPER (Special Section on Dependable Computing) Category: Keyword: fault tolerance, m-of-n codes, error detection codes, bidirectional communication,
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Long-Range Asynchronous On-Chip Link Based on Multiple-Valued Single-Track Signaling Naoya ONIZAWA Atsushi MATSUMOTO Takahiro HANYU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2012/06/01 Vol. E95-A No. 6 pp. 1018-1029 Type of Manuscript: PAPER Category: Circuit Theory Keyword: delay-insensitive, asynchronous circuits, multiple-valued current-mode (MVCM) circuits, Network-on-Chip (NoC), communication link,
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Design of an 8-nsec 72-bit-Parallel-Search Content-Addressable Memory Using a Phase-Change Device Satoru HANZAWA Takahiro HANYU
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2011/08/01 Vol. E94-C No. 8 pp. 1302-1310 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: content addressable memory, CAM, parallel search, phase-change device, one-hot coding, nonvolatile memory,
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Energy-Aware Multiple-Valued Current-Mode Sequential Circuits Using a Completion-Detection Scheme Hirokatsu SHIRAHAMA Takashi MATSUURA Masanori NATSUI Takahiro HANYU
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2010/08/01 Vol. E93-D No. 8 pp. 2080-2088 Type of Manuscript: Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing) Category: Multiple-Valued VLSI Technology Keyword: multiple-valued logic, current-mode circuit, adaptive current control, many-core processor,
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Highly Reliable Multiple-Valued One-Phase Signalling for an Asynchronous On-Chip Communication Link Naoya ONIZAWA Takahiro HANYU
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2010/08/01 Vol. E93-D No. 8 pp. 2089-2099 Type of Manuscript: Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing) Category: Multiple-Valued VLSI Technology Keyword: delay-insensitive, asynchronous circuits, multiple-valued current-mode (MVCM) circuits, Network-on-Chip (NoC), communication link,
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Transient Characteristic of Fabricated Magnetic Tunnel Junction (MTJ) Programmed with CMOS Circuit Masashi KAMIYANAGI Fumitaka IGA Shoji IKEDA Katsuya MIURA Jun HAYAKAWA Haruhiro HASEGAWA Takahiro HANYU Hideo OHNO Tetsuo ENDOH
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2010/05/01 Vol. E93-C No. 5 pp. 602-607 Type of Manuscript: Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices) Category: Flash/Advanced Memory Keyword: spin-transfer torque random access memory (STT-RAM), tunnel magnetoresistance (TMR), spin-injection, magnetic tunnel junction (MTJ), CMOS,
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Study of the DC Performance of Fabricated Magnetic Tunnel Junction Integrated on Back-End Metal Line of CMOS Circuits Fumitaka IGA Masashi KAMIYANAGI Shoji IKEDA Katsuya MIURA Jun HAYAKAWA Haruhiro HASEGAWA Takahiro HANYU Hideo OHNO Tetsuo ENDOH
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2010/05/01 Vol. E93-C No. 5 pp. 608-613 Type of Manuscript: Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices) Category: Flash/Advanced Memory Keyword: magnetic tunnel junction (MTJ), spin-transfer torque RAM (STT-RAM), tunnel magnetoresistance (TMR), magnetoresistive RAM (MRAM), current-induced magnetization switching,
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High-Throughput Bit-Serial LDPC Decoder LSI Based on Multiple-Valued Asynchronous Interleaving Naoya ONIZAWA Takahiro HANYU Vincent C. GAUDET
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2009/06/01 Vol. E92-C No. 6 pp. 867-874 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: error control coding, LDPC codes, sum-product algorithm, asynchronous data transfer, multiple-valued current-mode circuit,
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Power-Aware Asynchronous Peer-to-Peer Duplex Communication System Based on Multiple-Valued One-Phase Signaling Kazuyasu MIZUSAWA Naoya ONIZAWA Takahiro HANYU
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2008/04/01 Vol. E91-C No. 4 pp. 581-588 Type of Manuscript: Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories) Category: Keyword: delay-insensitive, dual-rail encoding, multiple-valued current-mode (MVCM) circuit, peer-to-peer communication,
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Highly Reliable Multiple-Valued Current-Mode Comparator Based on Active-Load Dual-Rail Operation Masatomo MIURA Takahiro HANYU
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2008/04/01 Vol. E91-C No. 4 pp. 589-594 Type of Manuscript: Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories) Category: Keyword: crosstalk, signal integrity, differential-pair circuit, multiple-valued logic,
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Design and Evaluation of a 5454-bit Multiplier Based on Differential-Pair Circuitry Akira MOCHIZUKI Hirokatsu SHIRAHAMA Takahiro HANYU
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/04/01 Vol. E90-C No. 4 pp. 683-691 Type of Manuscript: Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies) Category: Digital Keyword: differential-pair circuit, current-mode circuit, multiple-valued logic,
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Implementation of a High-Speed Asynchronous Data-Transfer Chip Based on Multiple-Valued Current-Signal Multiplexing Tomohiro TAKAHASHI Takahiro HANYU
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/11/01 Vol. E89-C No. 11 pp. 1598-1604 Type of Manuscript: Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies) Category: Keyword: network-on-chip (NoC), delay-insensitive, dual-rail encoding, globally asynchronous locally synchronous (GALS), point-to-point communication,
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Design of a Low-Power Quaternary Flip-Flop Based on Dynamic Differential Logic Akira MOCHIZUKI Hirokatsu SHIRAHAMA Takahiro HANYU
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/11/01 Vol. E89-C No. 11 pp. 1591-1597 Type of Manuscript: Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies) Category: Keyword: differential-pair circuit, current-mode circuit, multiple-valued logic, dynamic logic,
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Design and Evaluation of a NULL-Convention Circuit Based on Dual-Rail Current-Mode Differential Logic Naoya ONIZAWA Takahiro HANYU
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/11/01 Vol. E89-C No. 11 pp. 1575-1580 Type of Manuscript: Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies) Category: Keyword: asynchronous logic design, self-timed circuit, differential-pair circuit, delay insensitive,
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FOREWORD Takahiro HANYU
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/11/01 Vol. E89-C No. 11 pp. 1491-1491 Type of Manuscript: FOREWORD Category: Keyword:
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TMR-Based Logic-in-Memory Circuit for Low-Power VLSI Akira MOCHIZUKI Hiromitsu KIMURA Mitsuru IBUKI Takahiro HANYU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/06/01 Vol. E88-A No. 6 pp. 1408-1415 Type of Manuscript: Special Section PAPER (Special Section on Papers Selected from 2004 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2004)) Category: Keyword: MRAM, TMR device, dynamic current-mode logic, logic function, sum of absolute differences,
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Low-Power Motion-Vector Detection VLSI Processor Based on Pass-Gate Logic with Dynamic Supply-Voltage/Clock-Frequency Scaling Akira MOCHIZUKI Daisuke NISHINOHARA Takahiro HANYU
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2004/11/01 Vol. E87-C No. 11 pp. 1876-1883 Type of Manuscript: Special Section PAPER (Special Section on New System Paradigms for Integrated Electronics) Category: Keyword: CMOS pass gate, supply-voltage control, clock-frequency control, motion-vector detection, sum of absolute differences,
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Dynamically Function-Programmable Bus Architecture for High-Throughput Intra-Chip Data Transfer Akira MOCHIZUKI Takashi TAKEUCHI Takahiro HANYU
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2004/11/01 Vol. E87-C No. 11 pp. 1915-1922 Type of Manuscript: Special Section PAPER (Special Section on New System Paradigms for Integrated Electronics) Category: Keyword: common bus, bus width, distributed control, direct data transfer, direct memory access,
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Differential Operation Oriented Multiple-Valued Encoding and Circuit Realization for Asynchronous Data Transfer Tomohiro TAKAHASHI Naoya ONIZAWA Takahiro HANYU
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2004/11/01 Vol. E87-C No. 11 pp. 1928-1934 Type of Manuscript: Special Section PAPER (Special Section on New System Paradigms for Integrated Electronics) Category: Keyword: differential operation, delay-insensitive, dual-rail encoding, point-to-point communication,
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Low-Power Multiple-Valued Current-Mode Logic Using Substrate Bias Control Akira MOCHIZUKI Takahiro HANYU
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2004/04/01 Vol. E87-C No. 4 pp. 582-588 Type of Manuscript: Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies) Category: Keyword: differential-pair circuit, substrate bias control, dynamic power dissipation, threshold voltage, low-power VLSI, leakage current,
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Implementation of a DRAM-Cell-Based Multiple-Valued Logic-in-Memory Circuit Hiromitsu KIMURA Takahiro HANYU Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2002/10/01 Vol. E85-C No. 10 pp. 1814-1823 Type of Manuscript: PAPER Category: Optoelectronics Keyword: interconnection problem, pass-transistor network, functional pass gate, multiple-valued logic, content-addressable memory,
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Dynamic-Storage-Based Logic-in-Memory Circuit and Its Application to a Fine-Grain Pipelined System Hiromitsu KIMURA Takahiro HANYU Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2002/02/01 Vol. E85-C No. 2 pp. 288-296 Type of Manuscript: Special Section PAPER (Special Issue on High-Performance and Low-Power Microprocessors) Category: Low-Power Technologies Keyword: pass-transistor network, functional pass gate, precharge-evaluate logic, multiplier, signed-digit adder,
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Multiple-Valued Logic-in-Memory VLSI Architecture Based on Floating-Gate-MOS Pass-Transistor Logic Takahiro HANYU Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1999/09/25 Vol. E82-C No. 9 pp. 1662-1668 Type of Manuscript: Special Section PAPER (Special Issue on Integrated Electronics and New System Paradigms) Category: Non-Binary Architectures Keyword: pass-transistor network, floating-gate MOS transistor, logic-in-memory structure, Manhattan distance, flash EEPROM technology, four-valued full adder,
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Design and Implementation of a Low-Power Multiple-Valued Current-Mode Integrated Circuit with Current-Source Control Takahiro HANYU Satoshi KAZAMA Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1997/07/25 Vol. E80-C No. 7 pp. 941-947 Type of Manuscript: Special Section PAPER (Special Issue on New Concept Device and Novel Architecture LSIs) Category: Multiple-Valued Architectures Keyword: 54-bit multiplier, signed-digit arithmetic, differential logic circuit, threshold detector, source-coupled pair, multi-phase clocking,
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Design and Evaluation of a 4-Valued Universal-Literal CAM for Cellular Logic Image Processing Takahiro HANYU Manabu ARAKAKI Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1997/07/25 Vol. E80-C No. 7 pp. 948-955 Type of Manuscript: Special Section PAPER (Special Issue on New Concept Device and Novel Architecture LSIs) Category: Multiple-Valued Architectures Keyword: logic value conversion (LVC), floating-gate MOS transistor, threshold operation, single-transistor cell, fully parallel template matching,
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Quantum-Device-Oriented Multiple-Valued Logic System Based on a Super Pass Gate Xiaowei DENG Takahiro HANYU Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1995/08/25 Vol. E78-D No. 8 pp. 951-958 Type of Manuscript: PAPER Category: Computer Hardware and Design Keyword: multiple-valued logic, super pass gate, logic design, quantum devices, super pass transistor model,
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Low-Power 8-Valued Cellular Array VLSI for High-Speed Image Processing Takahiro HANYU Maho KUWAHARA Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1994/07/25 Vol. E77-C No. 7 pp. 1042-1048 Type of Manuscript: Special Section PAPER (Special Issue on Super Chip for Intelligent Integrated Systems) Category: Keyword: multiple-valued logic, dynamic circuits, small latency, cellular array, template matching,
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A High-Density Multiple-Valued Content-Addressable Memory Based on One Transistor Cell Satoshi ARAGAKI Takahiro HANYU Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/11/25 Vol. E76-C No. 11 pp. 1649-1656 Type of Manuscript: Special Section PAPER (Special Issue on LSI Memories) Category: Application Specific Memory Keyword: content-addressable memory, multiple-valued logic, floating-gate MOS, threshold function, logic-value conversion, relational search operation,
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Multiple-Valued Programmable Logic Array Based on a Resonant-Tunneling Diode Model Takahiro HANYU Yoshikazu YABE Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/07/25 Vol. E76-C No. 7 pp. 1126-1132 Type of Manuscript: Special Section PAPER (Special Issue on New Architecture LSIs) Category: Multiple-Valued Architectures and Systems Keyword: resonant-tunneling diode model, universal literal, load line method, multiple-valued PLA, wired logic, current-mode linear summation,
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3-D Object Recognition System Based on 2-D Chain Code Matching Takahiro HANYU Sungkun CHOI Michitaka KANEYAMA Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1993/06/25 Vol. E76-A No. 6 pp. 917-923 Type of Manuscript: Special Section PAPER (Special Section on Papers Selected from 1992 Joint Technical Conference on Circuits/Systems,Computers and Communications (JTC-CSCC'92)) Category: Methods and Circuits for Signal Processing Keyword: 3-D object recognition, chain code sequence, normalization, fast fourier transform (FFT), chain code matching, 3-D measurement,
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Prospects of Multiple-Valued VLSI Processors Takahiro HANYU Michitaka KAMEYAMA Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/03/25 Vol. E76-C No. 3 pp. 383-392 Type of Manuscript: INVITED PAPER (Special Issue on Multiple-Valued Integrated Circuits) Category: Keyword: submicron VLSI, interconnection delay, multiple-valued hardware algorithm, parallel VLSI processor, MVL arithmetic and logic circuits,
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Rule-Programmable Multiple-Valued Matching VLSI Processor for Real-Time Rule-Based Systems Takahiro HANYU Koichi TAKEDA Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/03/25 Vol. E76-C No. 3 pp. 472-479 Type of Manuscript: Special Section PAPER (Special Issue on Multiple-Valued Integrated Circuits) Category: Keyword: multiple-valued encoding, multiple-valued pattern matching, floating-gate MOS devices, programmable delta literal, fully parallel processing,
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A Design of a High-Density Multi-Level Matching Array Chip for Associative Processing Takahiro HANYU Hiroto ISHII Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1991/04/25 Vol. E74-C No. 4 pp. 918-928 Type of Manuscript: Special Section PAPER (Special Issue on LSI Memories) Category: ASIC Keyword:
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