Keyword : level-encoded dual-rail (LEDR) encoding


High-Throughput Partially Parallel Inter-Chip Link Architecture for Asynchronous Multi-Chip NoCs
Naoya ONIZAWA Akira MOCHIZUKI Hirokatsu SHIRAHAMA Masashi IMAI Tomohiro YONEDA Takahiro HANYU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/06/01
Vol. E97-D  No. 6 ; pp. 1546-1556
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
Asynchronous circuitsNetwork-on-Chip (NoC)burst-mode data transmissionlevel-encoded dual-rail (LEDR) encodingerror detectiondata retransmission
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