Keyword : Network-on-Chip (NoC)


Low-Cost Adaptive and Fault-Tolerant Routing Method for 2D Network-on-Chip
Ruilian XIE Jueping CAI Xin XIN Bo YANG 
Publication:   
Publication Date: 2017/04/01
Vol. E100-D  No. 4 ; pp. 910-913
Type of Manuscript:  LETTER
Category: Computer System
Keyword: 
Network-on-Chip (NoC)fault toleranceadaptive routingturn model
 Summary | Full Text:PDF

High-Throughput Partially Parallel Inter-Chip Link Architecture for Asynchronous Multi-Chip NoCs
Naoya ONIZAWA Akira MOCHIZUKI Hirokatsu SHIRAHAMA Masashi IMAI Tomohiro YONEDA Takahiro HANYU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/06/01
Vol. E97-D  No. 6 ; pp. 1546-1556
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
Asynchronous circuitsNetwork-on-Chip (NoC)burst-mode data transmissionlevel-encoded dual-rail (LEDR) encodingerror detectiondata retransmission
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Long-Range Asynchronous On-Chip Link Based on Multiple-Valued Single-Track Signaling
Naoya ONIZAWA Atsushi MATSUMOTO Takahiro HANYU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/06/01
Vol. E95-A  No. 6 ; pp. 1018-1029
Type of Manuscript:  PAPER
Category: Circuit Theory
Keyword: 
delay-insensitiveasynchronous circuitsmultiple-valued current-mode (MVCM) circuitsNetwork-on-Chip (NoC)communication link
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Hybrid Wired/Wireless On-Chip Network Design for Application-Specific SoC
Shouyi YIN Yang HU Zhen ZHANG Leibo LIU Shaojun WEI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/04/01
Vol. E95-C  No. 4 ; pp. 495-505
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
Network-on-Chip (NoC)on-chip wireless interconnection networkapplication-specific SoCmulti-core systemdesign automation
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Highly Reliable Multiple-Valued One-Phase Signalling for an Asynchronous On-Chip Communication Link
Naoya ONIZAWA Takahiro HANYU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/08/01
Vol. E93-D  No. 8 ; pp. 2089-2099
Type of Manuscript:  Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)
Category: Multiple-Valued VLSI Technology
Keyword: 
delay-insensitiveasynchronous circuitsmultiple-valued current-mode (MVCM) circuitsNetwork-on-Chip (NoC)communication link
 Summary | Full Text:PDF