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| Keyword : pipeline
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A Low-Latency Parallel Pipeline CORDIC
Hong-Thu NGUYEN Xuan-Thuan NGUYEN Cong-Kha PHAM | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2017/04/01
Vol. E100-C
No. 4 ;
pp. 391-398
Type of Manuscript:
Special Section PAPER (Special Section on Solid-State Circuit Design — Architecture, Circuit, Device and Design Methodology)
Category:
Keyword:
CORDIC, pipeline, low-latency, | | | Summary | Full Text:PDF | |
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A High Performance HEVC De-Blocking Filter and SAO Architecture for UHDTV Decoder
Jiayi ZHU Dajiang ZHOU Satoshi GOTO | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/12/01
Vol. E96-A
No. 12 ;
pp. 2612-2622
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword:
DBF, SAO, HEVC, pipeline, | | | Summary | Full Text:PDF | |
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A 64 Cycles/MB, Luma-Chroma Parallelized H.264/AVC Deblocking Filter for 4 K 2 K Applications
Weiwei SHEN Yibo FAN Xiaoyang ZENG | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2012/04/01
Vol. E95-C
No. 4 ;
pp. 441-446
Type of Manuscript:
Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology)
Category:
Keyword:
H.264/AVC, deblocking filter, pipeline, parallelism, 4 K2 K, | | | Summary | Full Text:PDF | |
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55-mW, 1.2-V, 12-bit, 100-MSPS Pipeline ADCs for Wireless Receivers
Tomohiko ITO Daisuke KUROSE Takeshi UENO Takafumi YAMAJI Tetsuro ITAKURA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2008/06/01
Vol. E91-C
No. 6 ;
pp. 887-893
Type of Manuscript:
Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category:
Keyword:
A/D, ADC, pipeline, low power, amplifier, pseudo-differential amplifier, I/Q sharing, | | | Summary | Full Text:PDF | |
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New Radix-2 to the 4th Power Pipeline FFT Processor
Jung-Yeol OH Myoung-Seob LIM | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2005/08/01
Vol. E88-C
No. 8 ;
pp. 1740-1746
Type of Manuscript:
Special Section PAPER (Special Section on Papers Selected from AP-ASIC 2004)
Category:
Keyword:
FFT, radix, pipeline, SDF, CSD, multiplier, | | | Summary | Full Text:PDF | |
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On Practical Implementation of the PIC Algorithm in Asynchronous CDMA Systems
Young Wha KIM Sung Ho CHO | Publication: IEICE TRANSACTIONS on Communications
Publication Date: 2003/08/01
Vol. E86-B
No. 8 ;
pp. 2508-2511
Type of Manuscript:
LETTER
Category: Wireless Communication Technology
Keyword:
CDMA, interference, cancellation, pipeline, | | | Summary | Full Text:PDF | |
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High-Level Synthesis of Pipelined Circuits from Modular Queue-Based Specifications
Maria-Cristina MARINESCU Martin RINARD | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A
No. 11 ;
pp. 2655-2664
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High Level Synthesis
Keyword:
asynchronous, modular, pipeline, term rewriting system, | | | Summary | Full Text:PDF | |
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Parallel Test Structure in Latch Based Asynchronous Pipeline
Jing-ling YANG Chiu-sing CHOY Cheong-Fat CHAN | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/11/25
Vol. E82-A
No. 11 ;
pp. 2527-2529
Type of Manuscript:
Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category:
Keyword:
asynchronous, pipeline, event logic, latch, test, | | | Summary | Full Text:PDF | |
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Invariant-Free Formal Verification of Pipelined and Superscalar Controls by Behavior-Covering and Partial Unfolding
Toru SHONAI Tsuguo SHIMIZU | Publication: IEICE TRANSACTIONS on Information and Systems
Publication Date: 1999/02/25
Vol. E82-D
No. 2 ;
pp. 376-388
Type of Manuscript:
PAPER
Category: Computer Hardware and Design
Keyword:
formal verification, processor, pipeline, superscalar, | | | Summary | Full Text:PDF | |
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Design Optimization by Using Flexible Pipelined Modules
Masahiro FUKUI Masakazu TANAKA Masaharu IMAI | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A
No. 12 ;
pp. 2521-2528
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Timing Verification and Optimization
Keyword:
pipeline, design tuning, module generation, | | | Summary | Full Text:PDF | |
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