A 10b 100 MS/s 1.4 mm2 56 mW 0.18 µm CMOS A/D Converter with 3-D Fully Symmetrical Capacitors

Byoung-Han MIN
Young-Jae CHO
Hee-Sung CHAE
Hee-Won PARK
Seung-Hoon LEE

IEICE TRANSACTIONS on Electronics   Vol.E89-C    No.5    pp.630-635
Publication Date: 2006/05/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e89-c.5.630
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Electronic Circuits
ADC,  CMOS,  low power,  on-chip references,  pipeline,  

Full Text: PDF>>
Buy this Article

This work proposes a 10b 100 MS/s 1.4 mm2 CMOS ADC for low-power multimedia applications. The proposed two-step pipeline ADC minimizes chip area and power dissipation at the target resolution and sampling rate. The wide-band SHA employs a gate-bootstrapping circuit to handle both single-ended and differential inputs of 1.2 Vp-p at 10b accuracy while the second-stage flash ADC employs open-loop offset sampling techniques to achieve 6b resolution. A 3-D fully symmetrical layout reduces the capacitor and device mismatch of the first-stage MDAC. The low-noise references are integrated on chip with optional off-chip voltage references. The prototype 10b ADC implemented in a 0.18 µm CMOS shows the maximum measured DNL and INL of 0.59LSB and 0.77LSB, respectively. The ADC demonstrates an SNDR of 53.7 dB, an SFDR of 61.5 dB, and the power dissipation of 56 mW at 100 MS/s.