Keyword : latch

A Low Power Soft Error Hardened Latch with Schmitt-Trigger-Based C-Element
Saki TAJIMA Nozomu TOGAWA Masao YANAGISAWA Youhua SHI 
Publication:   
Publication Date: 2018/07/01
Vol. E101-A  No. 7 ; pp. 1025-1034
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
soft error, low-power, latch, C-element, 
 Summary | Full Text:PDF
Analytical Stability Modeling for CMOS Latches in Low Voltage Operation
Tatsuya KAMAKARI Jun SHIOMI Tohru ISHIHARA Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/12/01
Vol. E99-A  No. 12 ; pp. 2463-2472
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
latch, low voltage design, stability modeling, 
 Summary | Full Text:PDF
Majority Gate-Based Feedback Latches for Adiabatic Quantum Flux Parametron Logic
Naoki TSUJI Naoki TAKEUCHI Yuki YAMANASHI Thomas ORTLEPP Nobuyuki YOSHIKAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2016/06/01
Vol. E99-C  No. 6 ; pp. 710-716
Type of Manuscript:  Special Section PAPER (Special Section on Cutting-Edge Technologies of Superconducting Electronics)
Category: 
Keyword: 
AQFP, superconducting circuits, Josephson integrated circuits, adiabatic logic, latch, 
 Summary | Full Text:PDF
MARK-OPT: A Concurrency Control Protocol for Parallel B-Tree Structures to Reduce the Cost of SMOs
Tomohiro YOSHIHARA Dai KOBAYASHI Haruo YOKOTA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2007/08/01
Vol. E90-D  No. 8 ; pp. 1213-1224
Type of Manuscript:  PAPER
Category: Database
Keyword: 
index, concurrency control, B-tree, parallel DB, latch, 
 Summary | Full Text:PDF
A 10-bit 800-Column Low-Power RAM Bank Including Energy-Efficient D-Flip-Flops for a Column-Parallel ADC
Shunsuke OKURA Tetsuro OKURA Bogoda A. INDIKA U.K. Kenji TANIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/02/01
Vol. E90-A  No. 2 ; pp. 358-364
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
CMOS, imager, column-parallel ADC, RAM bank, DFF, latch, buffer, energy efficient, 
 Summary | Full Text:PDF
Parallel Test Structure in Latch Based Asynchronous Pipeline
Jing-ling YANG Chiu-sing CHOY Cheong-Fat CHAN 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/11/25
Vol. E82-A  No. 11 ; pp. 2527-2529
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
asynchronous, pipeline, event logic, latch, test, 
 Summary | Full Text:PDF