A 0.9-V 12-bit 40-MSPS Pipeline ADC for Wireless Receivers

Tomohiko ITO  Tetsuro ITAKURA  

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E93-A   No.2   pp.395-401
Publication Date: 2010/02/01
Online ISSN: 1745-1337
DOI: 10.1587/transfun.E93.A.395
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
A/D,  ADC,  pipeline,  pseudodifferential amplifier,  I/Q sharing,  CMFB,  common-mode feedback,  

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Summary: 
A 0.9-V 12-bit 40-MSPS pipeline ADC with I/Q amplifier sharing technique is presented for wireless receivers. To achieve high linearity even at 0.9-V supply, the clock signals to sampling switches are boosted over 0.9 V in conversion stages. The clock-boosting circuit for lifting these clocks is shared between I-ch ADC and Q-ch ADC, reducing the area penalty. Low supply voltage narrows the available output range of the operational amplifier. A pseudo-differential (PD) amplifier with two-gain-stage common-mode feedback (CMFB) is proposed in views of its wide output range and power efficiency. This ADC is fabricated in 90-nm CMOS technology. At 40 MS/s, the measured SNDR is 59.3 dB and the corresponding effective number of bits (ENOB) is 9.6. Until Nyquist frequency, the ENOB is kept over 9.3. The ADC dissipates 17.3 mW/ch, whose performances are suitable for ADCs for mobile wireless systems such as WLAN/WiMAX.