New Radix-2 to the 4th Power Pipeline FFT Processor

Jung-Yeol OH  Myoung-Seob LIM  

IEICE TRANSACTIONS on Electronics   Vol.E88-C   No.8   pp.1740-1746
Publication Date: 2005/08/01
Online ISSN: 
DOI: 10.1093/ietele/e88-c.8.1740
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Papers Selected from AP-ASIC 2004)
FFT,  radix,  pipeline,  SDF,  CSD,  multiplier,  

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This paper proposes a new modified radix-24 FFT algorithm and an efficient pipeline FFT architecture based on this algorithm for OFDM systems. This pipeline FFT architecture has the same number of multipliers as that of the radix-22 algorithm. However, the multiplication complexity could be reduced by more than 30% by replacing one half of the programmable multipliers by the newly proposed CSD constant multipliers. From the synthesis simulations of a standard 0.35 µm CMOS SAMSUNG process, a proposed CSD constant complex multiplier achieved more than 60% area efficiency when compared to the conventional programmable complex multiplier. This promoted efficiency could be used to the design of a long length FFT processor in wireless OFDM applications, which needs more power and area efficiency.