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SEWD: A Cache Architecture to Speed up the Misaligned Instruction Prefetch
Joon-Seo YIM In-Cheol PARK Chong-Min KYUNG
IEICE TRANSACTIONS on Information and Systems
Publication Date: 1997/07/25
Print ISSN: 0916-8532
Type of Manuscript: LETTER
Category: Computer Hardware and Design
cache, microprocessor, pipeline,
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In microprocessors, reducing the cache access delay and the number of pipeline stall is critical to improve the system performance. In this paper, we propose a Separated Word-line Decoding (SEWD) cache to overcome the pipeline stall caused by the misaligned multi-words data or instruction prefetches which are placed over two cache lines. SEWD cache makes it possible to perform misaligned prefetch as well as aligned prefetch in one clock cycle. This feature is invaluable because the branch target addresses are very often misaligned (Percentage of misalignment in the cache is 8 to 13% for 16-byte caches). 8Kbyte SEWD cache chip was implemented in 0.8µm DLM CMOS process. It consists of 489,000 transistors on a die size of 0.8530.827cm2.