55-mW, 1.2-V, 12-bit, 100-MSPS Pipeline ADCs for Wireless Receivers

Tomohiko ITO  Daisuke KUROSE  Takeshi UENO  Takafumi YAMAJI  Tetsuro ITAKURA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E91-C   No.6   pp.887-893
Publication Date: 2008/06/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e91-c.6.887
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
A/D,  ADC,  pipeline,  low power,  amplifier,  pseudo-differential amplifier,  I/Q sharing,  

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Summary: 
For wireless receivers, low-power 1.2-V 12-bit 100-MSPS pipeline ADCs are fabricated in 90-nm CMOS technology. To achieve low-power dissipation at 1.2 V without the degradation of SNR, the configuration of 2.5 bit/stage is employed with an I/Q amplifier sharing technique. Furthermore, single-stage pseudo-differential amplifiers are used in a Sample-and-Hold (S/H) circuit and a 1st Multiplying Digital-to-Analog Converter (MDAC). The pseudo-differential amplifier with two-gain-stage transimpedance gain-boosting amplifiers realizes high DC gain of more than 90 dB with low power. The measured SNR of the 100-MSPS ADC is 66.7 dB at 1.2-V supply. Under that condition, each ADC dissipates only 55 mW.