Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2017/07/01 Vol. E100-ANo. 7pp. 1363-1373 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: multi-core systems, task allocation, fault patterns, task scheduling, reliability,
Fault Diagnosis and Reconfiguration Method for Network-on-Chip Based Multiple Processor Systems with Restricted Private Memories Masashi IMAITomohiro YONEDA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/12/01 Vol. E90-ANo. 12pp. 2790-2799 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: System Level Design Keyword: asynchronous circuits, scheduling, start times, and control steps,
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2003/12/01 Vol. E86-DNo. 12pp. 2601-2611 Type of Manuscript: Special Section PAPER (Special Issue on Dependable Computing) Category: Verification and Dependability Analysis Keyword: Level-oriented model, timed asynchronous circuits, formal verification, time Petri nets,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/12/01 Vol. E85-ANo. 12pp. 2684-2692 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis Keyword: logic synthesis, partial order reduction, timed circuits, modular synthesis,
rt SAAREPERA