Keyword : time Petri nets


Partial Order Reduction for Timed Circuit Verification Based on Level Oriented Model
Tomoya KITAI Yusuke OGURO Tomohiro YONEDA Eric MERCER Chris MYERS 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/12/01
Vol. E86-D  No. 12 ; pp. 2601-2611
Type of Manuscript:  Special Section PAPER (Special Issue on Dependable Computing)
Category: Verification and Dependability Analysis
Keyword: 
Level-oriented modeltimed asynchronous circuitsformal verificationtime Petri nets
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Framework of Timed Trace Theoretic Verification Revisited
Bin ZHOU Tomohiro YONEDA Chris MYERS 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/10/01
Vol. E85-D  No. 10 ; pp. 1595-1604
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Verification of VLSI)
Category: Verification
Keyword: 
timed trace theorytrace structurestime Petri netsformal verificationasynchronous circuits
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CTL Model Checking of Time Petri Nets Using Geometric Regions
Tomohiro YONEDA Hikaru RYUBA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/03/25
Vol. E81-D  No. 3 ; pp. 297-306
Type of Manuscript:  PAPER
Category: Fault Tolerant Computing
Keyword: 
CTLmodel checkingtime Petri netsgeometric regionformal verification
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